Dynamic Flash Memory Cells Using Refresh-Based Floating-Body Stabilization
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Solution Overview
Problem
Capacitive coupling between the word line and the floating body in capacitorless one-transistor DRAM (gain cell) leads to noise transmission, causing erroneous reading or rewriting of stored data, making it difficult to commercialize this type of memory cell.
Innovation Solution
A memory device with memory cells arranged in a row-column configuration, utilizing a vertical semiconductor body with controlled voltages applied to gate conductor layers and impurity layers to manage positive hole groups through impact ionization, including a refresh operation to stabilize the floating body potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless one-transistor DRAM (gain cell) is used, then device complexity is reduced and integration density is increased, but capacitive coupling noise between word line and floating body causes erroneous reading or rewriting
Solution Approach 1:
A plate line is introduced as an intermediary element between the word line and the floating body. The plate line acts as a shield that reduces direct capacitive coupling between the word line and floating body, thereby preventing noise transmission while maintaining the capacitorless one-transistor structure. This mediator structure allows the memory cell to retain its simplicity and high integration density while improving data storage stability.
2Area of stationary object
If vertical semiconductor body with surrounding gate is used, then integration density is increased, but manufacturing complexity increases
Solution Approach 1:
The invention transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure where the semiconductor body extends in the vertical direction and the gate surrounds it. This dimensional change allows multiple memory cells to be stacked vertically, significantly increasing integration density. The surrounding gate configuration is achieved through sequential gate formation processes that build upon standard planar fabrication techniques, making the complex 3D structure manufacturable with extended conventional processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces capacitive coupling noise, ensuring stable data storage and accurate reading/writing by maintaining a sufficient potential difference between '1' and '0' states, thereby enhancing the reliability of the memory device.
Implementation Method 1
accelerated electrons flowing from the source N+ layer 103 to the drain N+ layer 104 collide with the lattice of Si, and the kinetic energy lost at the time of collision generates electron-positive hole pairs (impact ionization phenomenon)
Data Source
AI summary
A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.