Memory Cell High-Voltage Drive Sharing for Denser FinFET MTPM
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Solution Overview
Problem
Existing multi-time programmable memories (MTPM) based on charge trap transistors (CTT) face challenges in achieving low program/erase cycles and memory density without additional processing or masking, particularly in FinFET processes.
Innovation Solution
The memory device incorporates both the memory cell and selection transistors driven by high voltage, with equal operating voltages, reducing the number of selection transistors and sharing well bias lines to minimize cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If both memory cell transistor and selection transistor are driven by high voltage with equal operating voltages, then memory cell density is enhanced and cell size is reduced, but transistor design complexity increases
Solution Approach 1:
The patent merges the drive voltage control for both selection transistor and memory cell transistor into a single high voltage supply system. Both transistors share the same high voltage operating conditions, eliminating the need for separate voltage control circuits and reducing overall device complexity despite the equal voltage requirement
Solution Approach 2:
The patent changes the operating voltage parameter from traditional low voltage to high voltage for both transistors. This parameter change enables reduced cell size and enhanced memory cell density while maintaining compatibility through unified voltage control, resolving the contradiction between size reduction and design complexity
2Area of moving object
If the number of selection transistors is reduced, then memory cell density increases, but programming and erasing efficiency may be compromised
Solution Approach 1:
The selection transistor is designed to perform multiple functions: it controls the flow of hot carriers during programming, manages the voltage distribution during erasing, and enables efficient read operations. This multi-functionality compensates for the reduced number of transistors, maintaining programming and erasing efficiency while increasing memory cell density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell density and reduces the size of the memory cell by minimizing the number of selection transistors, while maintaining efficient programming and erasing operations.
Implementation Method 1
The second high-k dielectric material includes a charge trapping layer
Data Source
AI summary
A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.