Nonvolatile Memory ML Voltage Tuning for V-NAND
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Solution Overview
Problem
As the number of word lines vertically stacked in a V-NAND increases, variations in channel hole sizes lead to inconsistent output voltages, affecting the performance and reliability of nonvolatile memory devices.
Innovation Solution
Implementing a C2C structure with a machine learning (ML) logic that uses an artificial neural network model to infer optimal voltages for memory cells, considering wafer location, reliability, and operational data to manage variations and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines vertically stacked in V-NAND is increased to achieve higher data storage capacity, then storage capacity increases, but variations in channel hole sizes cause inconsistent output voltages, worsening performance reliability
Solution Approach 1:
The patent applies local quality by implementing C2C structure that separately manufactures cell region and peripheral region on different wafers, allowing each region to be optimized independently. The machine learning logic then determines region-specific optimal voltages based on wafer location and manufacturing variations, ensuring each local area operates at its optimal performance level despite overall structural variations
Solution Approach 2:
The patent employs parameter changes by using machine learning to dynamically determine optimal voltages for different word lines based on multiple parameters including wafer location, manufacturing variations, and operational conditions. This allows the system to adapt voltage parameters to compensate for channel hole size variations, maintaining output voltage consistency across vertically stacked word lines
2Productivity
If C2C structure with machine learning logic is implemented to optimize voltages, then voltage optimization and performance improve, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into separate cell region and peripheral region manufactured on different wafers, then connected through C2C structure. The machine learning logic is integrated as a separate functional block within the peripheral region, allowing voltage optimization functionality to be added without redesigning the entire memory structure
Solution Approach 2:
The patent uses machine learning logic as an intermediary component that receives input parameters (wafer location, manufacturing data) and outputs optimized voltage values. This intermediary layer mediates between the physical hardware variations and the electrical operation, translating manufacturing variations into compensating voltage adjustments without requiring direct structural modifications to the memory cells
Data Source
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AI summary
A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.