3D NAND Memory Integration via Vertical Stacking and Shared Interconnects
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the high cost of advanced equipment required for fine pattern formation, and three-dimensional devices face challenges in reducing fabrication costs while ensuring reliable product characteristics for mass production.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a NAND-type string of nonvolatile memory cells with vertically-stacked sub-strings, string and ground selection transistors, and conductive plugs on an electrically insulating layer, along with a sense amplifier and column decoder, which reduces horizontal area occupation and enhances integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory devices use fine pattern forming technology to increase integration, then integration density is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory devices to three-dimensional vertically-stacked memory structures. Multiple memory cell layers are stacked vertically with select transistors positioned between layers, enabling higher integration density without requiring finer horizontal patterning. This vertical stacking approach achieves increased capacity while avoiding the expensive fine pattern forming equipment needed for traditional 2D scaling.
2Ease of manufacture
If three-dimensional memory devices are designed to reduce fabrication cost, then manufacturing cost decreases, but integration density may be compromised
Solution Approach 1:
The memory device is segmented into multiple functional layers stacked vertically: memory cell layers, select transistor layers, and interlayer insulating layers. Each layer performs a specific function and can be fabricated using standard planar processes, avoiding the need for complex 3D fabrication equipment. This segmentation allows cost-effective manufacturing while achieving high integration through vertical stacking.
Solution Approach 2:
The select transistors positioned between memory cell layers serve dual functions: they select specific memory strings for read/write operations and act as ground selection transistors. This multi-functionality reduces the total number of transistors needed compared to having separate select and ground select transistors, thereby improving integration density without increasing fabrication complexity.
3Quantity of substance
If vertically-stacked memory cell layers are implemented, then integration density increases, but device complexity increases due to additional interconnections
Solution Approach 1:
Adjacent memory cell layers are merged into NAND-type memory strings that extend vertically through multiple layers. The bit lines and source lines are shared across multiple memory cell layers, reducing the total number of interconnections needed. This merging approach simplifies the interconnection structure while maintaining high integration density through vertical stacking.
Data Source
AI summary
Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate.