3D-NAND MONOS Memory String Structure for Oxide-Semiconductor Erase
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Solution Overview
Problem
Existing methods for erasing 3D-NAND memory devices using oxide semiconductors are ineffective due to the wide bandgap of oxide semiconductors, preventing hole injection and hindering erase operations.
Innovation Solution
A semiconductor device structure is designed with concentric layers of oxide semiconductor, insulators, and conductors, where the insulator thickness varies to facilitate efficient hole injection and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor is used for body portion, then device reliability is improved, but hole injection becomes impossible due to wide bandgap
Solution Approach 1:
A P-type semiconductor layer is introduced as an intermediary between the p-type polysilicon contact and the oxide semiconductor body portion. This intermediate layer serves as a bridge that enables hole injection from the polysilicon contact to the oxide semiconductor by providing a stepped energy barrier structure, where the P-type semiconductor has intermediate energy levels that facilitate carrier transport across the wide bandgap material.
Solution Approach 2:
The energy band parameters are modified by introducing the P-type semiconductor layer with specific doping concentrations and material properties. By changing the material parameters (bandgap, doping level) of the intermediate layer, the energy barrier for hole injection is optimized to enable efficient erase operations while maintaining the reliability benefits of oxide semiconductor.
2Ease of manufacture
If simple replacement from polysilicon to oxide semiconductor is performed, then manufacturing process is simplified, but erase operation becomes impossible
Solution Approach 1:
The body portion structure is segmented into multiple functional layers: the oxide semiconductor layer for reliability and the P-type semiconductor layer for hole injection functionality. This segmentation allows each layer to perform its specific function optimally - the oxide semiconductor provides stability while the P-type layer enables erase operations - while still using standard polysilicon contact structures for manufacturing compatibility.
3Stability of the object's composition
If oxide semiconductor with wide bandgap is used, then device stability is improved, but hole generation and injection mechanisms fail
Solution Approach 1:
The P-type semiconductor layer acts as a mediator that enables hole generation and injection into the oxide semiconductor. This intermediate layer provides the necessary energy states for hole generation and transport, overcoming the wide bandgap limitation while preserving the stability benefits of the oxide semiconductor body portion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enables high-speed, reliable, and high-capacity memory operations in 3D-NAND devices, overcoming the limitations of using oxide semiconductors.
Implementation Method 1
the first insulator is thicker than the third insulator
Data Source
AI summary
A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.