3D NAND Neuromorphic Memory Mapping for Low-Power Neural Computing
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Solution Overview
Problem
Existing neuromorphic technologies face challenges in efficiently utilizing the high integration capabilities of 3D NAND flash memory due to structural limitations, leading to excessive burden on peripheral circuits and high power consumption during neural network operations.
Innovation Solution
A neuromorphic memory device is proposed that maps neural network layers to string selection lines in a one-to-one basis, utilizing a three-dimensional memory element with bit lines, word lines, and string selection lines to configure network topologies, enabling efficient weight storage and low-power operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing synapse array technology uses cross-point type array or NOR/AND flash arrays with word line input method, then vector matrix multiplication can be performed, but the number of blocks required increases significantly when the number of input signals is in the hundreds to thousands, placing great burden on peripheral circuits
Solution Approach 1:
The patent introduces a third dimension by utilizing the stack direction of 3D NAND flash memory for string selection lines. Instead of only using word lines and bit lines in a 2D cross-point array, the invention adds vertical stacking of multiple NAND cell layers, where each layer can be independently selected by string selection lines. This dimensional expansion allows parallel access to multiple blocks simultaneously, reducing the burden on peripheral circuits while maintaining high computation capability.
Solution Approach 2:
The patent divides the neural network computation task across multiple segmented blocks in the 3D NAND structure. Each block can be independently accessed and processed in parallel through the multi-layer stack architecture. By segmenting the computation across spatial blocks and temporal cycles, the system handles large numbers of input signals without overloading peripheral circuits, as each block processes a subset of the overall computation.
2Area of stationary object
If 3D NAND flash memory is used with high cell integration, then area efficiency is improved, but structural limitations prevent efficient utilization due to serial connection of memory cells in internal strings
Solution Approach 1:
The patent implements dynamic reconfiguration capability by allowing the system to adaptively assign different blocks and layers to different neural network layers based on computational requirements. The string selection lines can be dynamically activated to access specific blocks, and the system can reconfigure which blocks are used for weight storage versus computation at different times. This dynamic adaptability overcomes the structural limitations of serial connections by flexibly utilizing the available memory resources.
Solution Approach 2:
The patent makes the 3D NAND flash memory structure multi-functional by enabling it to serve both as high-density weight storage and as a parallel computation engine. The same physical structure that provides high integration density is also configured to support multiple neural network layers and different computation modes through the string selection mechanism. This universality allows the system to maintain high area efficiency while achieving the versatility needed for various neural network configurations.
3Productivity
If existing methods require simultaneous access to a large number of blocks, then neural network operations can be performed, but power consumption increases due to excessive peripheral circuit activity
Solution Approach 1:
The patent employs periodic action by dividing neural network computation into sequential cycles, where each cycle processes a subset of neurons or synapses. Instead of simultaneously accessing all blocks in parallel, the system periodically activates different blocks in a time-multiplexed manner. This approach maintains high computational throughput by utilizing the high-speed access capability when needed, while reducing average power consumption by keeping peripheral circuits inactive during idle periods between cycles.
Data Source
AI summary
The present disclosure relates to a neuromorphic memory device and a neuromorphic system using the same. The neuromorphic memory device includes a three-dimensional memory element including NAND cell strings, a bit line that outputs an output signal, forms a first axis of the three-dimensional memory element, and connects NAND cells existing on the same first axis among the NAND cell strings, a word line that receives an input signal, forms a second axis of the three-dimensional memory element, and connects NAND cells existing on the same second axis among the NAND cell strings, and a string selection line that forms a layer of an artificial intelligence neural network, forms a third axis of the three-dimensional memory element, and connects NAND cells existing on the same third axis among the NAND cell strings by intersecting the bit line and the word line.