Read-Only Memories TRIZ Cases
- Memory Array DAC Using Subthreshold Access Transistors
Temperature-compensated gate voltages improve accuracy, while a dedicated DAC region helps prevent memory data disturb.
- Sense Amplifier Circuit Using Capacitive Voltage-Difference Amplification
Precharged capacitors amplify small data-line voltage differences, improving sensing accuracy and speed margins despite amplifier offset.
- Memory Device Program-State Skipping for Faster Multi-Pass Programming
A segmented two-pass scheme skips selected program states first, reducing NAND Flash program cycles and overall program time.
- NAND Flash Erase Voltage and Verify Scheduling Across Blocks
A memory controller schedules erase voltage application and verify operations across blocks to reduce standby time and improve throughput.
- Memory Array Connections Through Control Gates for Dense Routing
This case routes conductive connections through control gates to reduce interconnect length and complexity in dense memory arrays.
- Flash Memory Cell Erase Sequencing to Prevent Over-Erased Leakage
A staged erase, post-program, and verify sequence recovers over-erased cells and protects flash data integrity during power drops.
- Memory Bit Line Equalization for Low-Power Intermediate Pre-Charge
A voltage equalizing circuit lowers double-pumping power by avoiding full bit-line pre-charge while supporting stable memory operations.
- Nonvolatile Memory Erase Control to Prevent Open-Block Over-Erasure
This case uses block-aware pre-program voltage levels during erase loops to preserve threshold voltage distributions and retention.
- Semiconductor Device Capacitive Voltage Boosting for NAND Flash
This semiconductor circuit uses capacitive coupling to boost word line switch voltage, reducing core area and power consumption.
- 3D NAND Neuromorphic Memory Mapping for Low-Power Neural Computing
String-selection mapping uses 3D NAND layers to reduce block access and peripheral-circuit burden in neuromorphic computing.
- Retracted Word Lines for Multilayer Memory Charge Control
This multilayer storage design redirects charge and uses selection-gate pre-charging to improve memory-cell electrical behavior.
- Semiconductor Memory Decoder Control for Wider Set–Reset Margins
Selective biasing of word and bit lines adjusts threshold voltage in target cells, widening state margins for stable data retention.
- Semiconductor Memory Erase Verification with Maintained Word-Line Voltage
A controller maintains word-line voltage between memory-string checks, reducing repeated discharge and speeding block erase verification.
- Non-Volatile Memory Word-Line Boosting for Fast, Reliable Reads
A staged voltage boost rapidly charges unselected word lines, then limits them near pass voltage for reliable memory reads.
- Floating-Gate Memory Circuit Merging Read and Coupling Transistors
Merging the read function with a coupling transistor reduces parasitic capacitance and read offsets while extending memory retention time.
- Multi-Plane Memory Programming With Selective Verify Operations
Selective plane verification cuts redundant checks and power use during flash memory writes.
- Memory Source Line Segmentation for Low-Leakage Writes
On-die clamp and ground memory cells dynamically bias source line segments, reducing leakage and unselected-cell disturbances during writes.