Retracted Word Lines for Multilayer Memory Charge Control
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in optimizing the electrical characteristics of memory cell transistors due to interference between adjacent memory cells, particularly in multi-layered structures where charge distribution can affect neighboring cells during write operations.
Innovation Solution
The semiconductor storage device employs a unique design with alternating conductive and insulating layers, featuring retracted portions in the word lines to minimize charge interference by directing charge concentration away from adjacent memory cells, and utilizes different selection gate lines for channel pre-charging to ensure optimal voltage conditions during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive layers and insulating layers are alternately stacked to form multi-layered structure, then storage capacity is improved, but charge interference between adjacent memory cells increases
Solution Approach 1:
The patent introduces a retracted portion structure in the word line that acts as an intermediary element between adjacent memory cells. This retracted portion directs charge concentration away from adjacent memory cells during write operations, reducing charge interference while maintaining the multi-layered storage structure.
Solution Approach 2:
The patent applies local quality modification by creating retracted portions at specific locations in the word line structure. These retracted portions are positioned to locally alter charge distribution patterns, directing charges away from adjacent memory cells only where interference occurs, while maintaining normal operation in other regions.
2Productivity
If word lines are extended to cover adjacent memory cells, then write operation coverage is improved, but charge interference to adjacent cells increases
Solution Approach 1:
The patent segments the word line structure by introducing retracted portions that create distinct regions. The word line is divided into main body portions and retracted portions, where the retracted portions specifically function to manage charge distribution and prevent interference with adjacent memory cells during write operations.
Solution Approach 2:
The retracted portions serve as intermediary structures between the word line and adjacent memory cells. These portions mediate the charge interaction by directing charge concentration away from adjacent cells, allowing the word line to maintain extended coverage without causing harmful interference.
3Ease of manufacture
If standard word line structure is used, then manufacturing simplicity is maintained, but adjacent interference cannot be effectively reduced
Solution Approach 1:
The patent introduces dynamic structural elements through the retracted portions in the word line. These retracted portions are formed through selective removal processes that create three-dimensional structures capable of dynamically managing charge distribution during write operations, improving upon the flat standard word line structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar word line structure to a three-dimensional structure with retracted portions. This dimensional change allows the word line to actively manage charge distribution in the vertical dimension, directing charges away from adjacent memory cells while maintaining manufacturing feasibility through established semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor storage device according to one embodiment includes a multi-layered body and a columnar body. The multi-layered body includes a plurality of gate electrode layers and a plurality of insulating layers.