Memory Array Connections Through Control Gates for Dense Routing
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Solution Overview
Problem
As memory cell density increases in memory devices, routing interconnections within a given device area becomes difficult, leading to challenges in efficiently connecting memory cells and circuitry.
Innovation Solution
The implementation of connections that go through control gates, allowing for improved routing of interconnections within the memory array by reducing the number and length of connections, and optimizing the fabricating process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density increases for a given device area, then storage capacity is improved, but routing interconnections becomes more difficult
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by having connections pass vertically through control gates. This dimensional change allows interconnections to route through the depth of the device rather than only in the plane, significantly reducing routing complexity while maintaining high memory cell density.
Solution Approach 2:
The patent implements nested routing where connections are embedded within the control gate structures themselves. The connections pass through openings in the control gates, effectively nesting the interconnection paths within the existing gate architecture, thereby simplifying overall device complexity.
2Productivity
If connections are routed through control gates, then interconnection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming openings in control gates during the gate fabrication process itself, before the routing connections are established. This preliminary preparation of connection paths through the gates simplifies subsequent manufacturing steps and improves overall ease of manufacture.
Solution Approach 2:
The patent merges the control gate fabrication process with the connection formation process. By combining these two operations into a single integrated process flow, the patent improves interconnection efficiency while actually reducing overall manufacturing complexity rather than increasing it.
3Ease of manufacture
If traditional routing methods are used, then manufacturing process is simpler, but device area increases
Solution Approach 1:
By moving from two-dimensional planar routing to three-dimensional routing through control gates, the patent achieves more efficient space utilization. This dimensional transition reduces the overall device area required while maintaining manufacturing simplicity through integrated process design.
Data Source
AI summary
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.