Memory Bit Line Equalization for Low-Power Intermediate Pre-Charge
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Solution Overview
Problem
Conventional memory systems require excessive power consumption during double pumping operations due to the need to pre-charge bit lines to the supply voltage level, making it impractical for high-density semiconductor applications.
Innovation Solution
Implementing circuits that skip full pre-charging of bit lines by equalizing voltage between bit line pairs during intermediate pre-charge, using transistors to set the voltage to a level between supply and ground, reducing power consumption while maintaining stable memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are fully pre-charged to supply voltage level during double pumping operations, then memory cell operations are stable and reliable, but power consumption becomes excessive
Solution Approach 1:
The patent applies partial pre-charge action by equalizing bit line voltages to an intermediate voltage level (Veq) rather than fully charging to supply voltage (VDD). This partial charging approach reduces the voltage swing and associated power consumption while maintaining sufficient voltage difference for reliable memory cell operation during double pumping sequences
Solution Approach 2:
The patent changes the voltage parameter from full supply voltage (VDD) to an intermediate equalized voltage (Veq) during intermediate pre-charge operations. This parameter modification reduces the energy required for voltage transitions while preserving the functional requirements for memory cell stability and operation reliability
2Stability of the object's composition
If full pre-charging is performed between memory operations, then bit line voltage stability is maintained, but power consumption increases making high-density applications impractical
Solution Approach 1:
The patent performs partial pre-charge action by equalizing bit line voltages to an intermediate level rather than fully charging to supply voltage. This partial action maintains sufficient voltage stability for memory operations while significantly reducing the power consumption that would otherwise prevent high-density memory applications
3Use of energy by moving object
If intermediate pre-charge equalization is used instead of full pre-charging, then power consumption is reduced, but bit line voltage level must be carefully controlled
Solution Approach 1:
The patent introduces an intermediate voltage equalization mechanism that acts as a mediator between full pre-charge and no pre-charge states. This intermediary approach provides controlled voltage equalization to an intermediate level, reducing power consumption while managing voltage control complexity through structured circuit implementation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces overall power consumption, enabling higher density memory circuits with improved performance and efficiency in semiconductor technology.
Implementation Method 1
a voltage equalizing device configured to equalize the voltage of the first bit line and the second bit line following the write operation and prior to a second memory operation for the memory cell
Data Source
AI summary
Memory devices, circuits, and a method of operating the same are disclosed. In one aspect, a memory device includes a memory cell coupled between a first bit line and a second bit line. The memory cell includes a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation. The memory cell includes a voltage equalizing device configured to equalize the voltage of the first bit line and the second bit line following the write operation and prior to a second memory operation for the memory cell.