Flash Memory Cell Erase Sequencing to Prevent Over-Erased Leakage
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Solution Overview
Problem
Flash memory devices face issues with over-erased cells causing leakage current due to suspended erase operations, leading to incorrect data readouts, particularly when power drops occur before post-programming is completed.
Innovation Solution
A method involving multiple erase operations with incremental bias voltage adjustments and post-programming steps to ensure all memory cells meet specific verify voltage thresholds, ensuring complete erasure and minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase operation is performed on a block of memory cells, then the erase operation is completed quickly, but over-erased cells cause leakage current and data integrity issues
Solution Approach 1:
The erase operation is divided into multiple incremental steps with increasing erase voltages. The first erase operation uses a first erase voltage, and the second erase operation uses a second erase voltage higher than the first. This segmentation allows gradual erasure while verifying intermediate results, preventing over-erasure and ensuring data integrity while maintaining reasonable erase speed.
Solution Approach 2:
A verify operation is performed after the first erase operation to check whether memory cells have been properly erased before proceeding to the second erase operation. This preliminary verification prevents unnecessary high-voltage erasure operations and ensures that cells are erased to the appropriate threshold, maintaining both speed and reliability.
2Reliability
If the erase voltage is increased to ensure complete erasure, then all cells are properly erased, but the risk of over-erasing cells increases causing leakage current
Solution Approach 1:
The erase voltage parameter is changed incrementally across two operations. The first erase operation uses a lower first erase voltage, and the second erase operation uses a higher second erase voltage. This parameter progression allows cells to be erased to the appropriate threshold without exceeding it, ensuring complete erasure while preventing over-erasure and leakage current.
Solution Approach 2:
A verify operation provides feedback after the first erase operation to determine whether memory cells have been properly erased. Based on this feedback, the system decides whether to proceed with the second erase operation at a higher voltage. This feedback mechanism ensures that cells are erased to the correct threshold, preventing both under-erasure and over-erasure.
3Reliability
If a post-program operation is performed to recover over-erased cells, then cell threshold voltages are recovered, but the overall erase time increases and power consumption increases
Solution Approach 1:
The erase voltage is dynamically adjusted based on the verify results. The first erase operation uses a lower voltage, and if verification shows cells are not fully erased, a second erase operation uses a higher voltage. This dynamic adjustment eliminates the need for post-program recovery operations while achieving complete erasure, reducing total time and power consumption.
Solution Approach 2:
The verify operation is performed preliminarily after the first erase operation to check erasure completeness before proceeding to the second erase operation. This preliminary verification prevents the need for subsequent post-program recovery operations, as the incremental erase approach with verification ensures cells are erased to the appropriate threshold from the beginning.
4Reliability
If incremental erase operations with verification are performed, then over-erased cells are prevented, but the number of operations increases
Solution Approach 1:
The erase operation is segmented into two distinct operations with different voltages, with a verify operation in between. This segmentation into manageable steps with verification points ensures reliability and prevents over-erasure, while the structured two-step approach keeps the complexity manageable and predictable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively recovers over-erased cells, maintaining data integrity by ensuring all cells meet required threshold voltages, even in the presence of power interruptions.
Implementation Method 1
The erase operation of a MOSFET is conducted by applying a high positive voltage (e.g. 8 volts) into the common p-well of the MOSFET and a strong negative voltage (e.g. −10 volts) is applied to the gate of the MOSFET causing electrons to be repelled from the floating gate of the MOSFET device
Implementation Method 2
The program operation of a MOSFET is conducted by applying a high positive voltage (e.g. 9 volts) into the gate of the MOSFET and a lower positive voltage (e.g. 4 volts) into the drain of the MOSFET causing electrons to fill up the floating gate of the MOSFET device
Data Source
AI summary
The disclosure is directed to a method of erasing memory cells of a flash memory device including performing first erase operation to erase a block of memory cells of the flash memory device; increasing the erase bias voltage in a stepping manner until a lower edge of a distribution of threshold voltages of the block of memory cells is lower than an erase low side verify voltage; performing a first post program operation until the lower edge of the distribution of threshold voltages of the block of memory cells is higher than a post verify voltage; and performing a second erase operation to determine whether an upper edge of the distribution of threshold voltages of the block of memory cells is lower than an erase high side verify voltage.