Floating-Gate Memory Circuit Merging Read and Coupling Transistors
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Solution Overview
Problem
Existing floating-gate memory structures suffer from large read offsets due to the use of small read transistors with parasitic capacitances, leading to reduced memory retention time and statistical uncertainty in voltage measurements.
Innovation Solution
Configuring one MOS transistor with a large floating gate as a read transistor, eliminating the need for a separate read transistor, thereby increasing capacitive coupling and reducing read offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a small read transistor is used to read the floating-gate memory structure, then the read operation can be performed, but the parasitic capacitance of the small read transistor causes large read offsets and reduces memory retention time
Solution Approach 1:
The patent merges the read transistor with one of the existing coupling transistors (either the first PMOS transistor with capacitance Cc or the second PMOS transistor with capacitance Ct). By combining these functions into a single transistor, the parasitic capacitance is reduced and the read offset is minimized, thereby improving voltage reading accuracy while maintaining read operation capability.
2Productivity
If a separate read transistor is used in the floating-gate memory structure, then the memory can be read, but the parasitic capacitance increases the read offset and reduces memory retention time
Solution Approach 1:
The patent combines the read function with the existing coupling transistors by configuring one of them as the read transistor. This eliminates the need for a separate read transistor, reducing parasitic capacitance and minimizing the read offset, thereby extending memory retention time while preserving the memory read function.
Solution Approach 2:
The patent makes one of the coupling transistors serve dual purposes: it functions as both a coupling transistor for charge transfer and as the read transistor for voltage sensing. This multi-functionality reduces the total number of components and their associated parasitic capacitances, improving memory retention time.
3Reliability
If small coupling capacitance transistors are used to maximize coupling, then the coupling between input terminals and floating gate is improved, but the read offset increases due to the small size of the read transistor
Solution Approach 1:
The patent merges the read transistor function with one of the coupling transistors, allowing the coupling capacitance to be optimized independently of the read transistor size. This resolves the contradiction by enabling strong capacitive coupling through the dedicated coupling transistor while the merged read transistor provides accurate voltage sensing with minimal read offset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces read offsets and enhances memory retention time by improving capacitive coupling, allowing for more accurate and stable voltage readings.
Implementation Method 1
the floating gate FG is charged by tunnel effect by coupling a programming voltage applied at a first input terminal T of the first PMOS transistor 1 or at a second input terminal B of the second PMOS transistor 2
Data Source
AI summary
An electronic circuit having a floating-gate memory structure, which includes from a first input terminal (T) a first MOS type transistor (1) with a large floating gate (FG), and from a second input terminal (B) a second MOS type transistor (2) with a smaller floating gate (FG) than the first MOS transistor (1). The first MOS transistor (1) is connected in series via its floating gate (FG) to the floating gate (FG) of the second MOS transistor (2). The electronic circuit is arranged so as to read and charge the floating-gate memory structure. The first MOS transistor is converted to act directly as a read transistor of the floating-gate memory structure.