Semiconductor Memory Erase Verification with Maintained Word-Line Voltage
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Solution Overview
Problem
The increasing capacity of semiconductor memory devices leads to a prolonged erase process operation time, particularly in erase verify operations, which negatively impacts performance.
Innovation Solution
The semiconductor memory device employs a controller to manage erase operations by applying an erase voltage to word lines, addressing memory strings with selection transistors, and using a sense amplifier to read data, while maintaining the word line voltage for subsequent strings, thereby reducing the need for repeated discharging and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of semiconductor memory devices is increased, then the storage capability is improved, but the erase process operation time is prolonged
Solution Approach 1:
The memory block is divided into multiple memory strings (first memory string, second memory string, etc.), each with its own selection transistors. This segmentation allows independent addressing and verification of different strings, enabling parallel processing operations and reducing the total erase verify time despite increased capacity.
Solution Approach 2:
The controller maintains the word line voltage at the erase verify voltage level after completing the erase operation, before initiating the next memory string verification. This preliminary maintenance of voltage eliminates the need for repeated discharging and re-charging cycles, directly reducing the erase process time while supporting higher capacity devices.
2Reliability
If the erase verify operation is performed for each memory string, then the data erasure reliability is improved, but the overall erase time is prolonged
Solution Approach 1:
The word line voltage is maintained continuously at the erase verify voltage level across multiple memory string verifications without intermediate discharging. This continuous voltage maintenance allows seamless transition between string verifications, ensuring reliable erase verification for each string while minimizing the total time required for the erase process.
Solution Approach 2:
The controller prepares the word line voltage in advance at the required erase verify level before addressing each subsequent memory string. This preliminary voltage preparation eliminates waiting time and ensures that verification can proceed immediately, maintaining high reliability while reducing overall erase time.
Data Source
AI summary
A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality ofA memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.