Multi-Plane Memory Programming With Selective Verify Operations
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Solution Overview
Problem
Existing flash memory devices face inefficiencies in power consumption during data write operations due to repetitive verify operations across multiple memory cell planes, leading to unnecessary energy expenditure.
Innovation Solution
A memory device with multiple memory cell planes that performs multi-plane program operations, utilizing a control logic to adjust the number of verify operations based on the determination results of previous program loops, allowing some planes to skip verify operations when determined to be program-passed, thereby optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify operations are performed repeatedly across all memory cell planes, then program reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the verify operation behavior across different memory cell planes based on their individual program status. The control logic identifies which planes have passed programming verification and which have failed, then selectively applies verify operations only to planes that need them. This localized approach ensures that planes already verified do not undergo redundant power-consuming operations, while planes requiring verification continue to receive appropriate operations, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent implements partial action by performing verify operations on only a subset of memory cell planes rather than all planes. The control logic determines the exact subset of planes that require verification based on program pass/fail status from previous operations. This partial verification approach maintains sufficient program reliability for planes that need it while avoiding excessive power consumption from verifying planes that have already passed, directly addressing the technical contradiction.
2Reliability
If verify operations are performed on all memory cell planes, then program verification completeness is improved, but operation time increases
Solution Approach 1:
The patent applies local quality by differentiating the verify operation behavior across different memory cell planes based on their individual program status. The control logic identifies which planes have passed programming verification and which have failed, then selectively applies verify operations only to planes that need them. This localized approach ensures that planes already verified do not undergo redundant power-consuming operations, while planes requiring verification continue to receive appropriate operations, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent implements partial action by performing verify operations on only a subset of memory cell planes rather than all planes. The control logic determines the exact subset of planes that require verification based on program pass/fail status from previous operations. This partial verification approach maintains sufficient program reliability for planes that need it while avoiding excessive power consumption from verifying planes that have already passed, directly addressing the technical contradiction.
3Productivity
If multi-plane program operations are performed, then data write throughput is improved, but power consumption increases
Solution Approach 1:
The patent applies segmentation by dividing the multi-plane program operation into independent controllable segments. Each memory cell plane can be managed independently by the control logic, which tracks the program status of each plane separately. This segmentation allows the system to perform parallel program operations across multiple planes for high throughput, while simultaneously enabling selective verification of only those planes that require it, thus resolving the contradiction between productivity and power consumption.
Solution Approach 2:
The patent implements partial action by performing verify operations on only a subset of memory cell planes rather than all planes. The control logic determines the exact subset of planes that require verification based on program pass/fail status from previous operations. This partial verification approach maintains sufficient program reliability for planes that need it while avoiding excessive power consumption from verifying planes that have already passed, directly addressing the technical contradiction.
Data Source
AI summary
A memory device includes control logic configured to control memory cell planes based on a determination result, wherein the control logic is further configured to, in response to the determination result for a first program loop in which a first memory cell plane is determined to be program-passed and a second memory cell plane is determined to be program-failed through a first verify voltage for a first program state, control the memory cell planes so that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop performed sequentially after the first program loop.