Semiconductor Memory Decoder Control for Wider Set–Reset Margins
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining a wide margin between the set and reset states of memory cells, which affects data reliability, particularly in nonvolatile memory devices like NAND type memories and next-generation memories.
Innovation Solution
The semiconductor device employs a control circuit to generate specific bias voltage combinations and control decoders to manage word and bit lines, enhancing the margin between the set and reset states through controlled voltage differences and time intervals, ensuring high data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normal write operation is performed on memory cells, then the memory cell transitions to a set state or reset state, but the margin between set state and reset state becomes insufficient for high-reliability applications
Solution Approach 1:
The patent applies preliminary action by performing an additional write operation after the normal write operation to further adjust the threshold voltage of memory cells requiring high reliability. This preliminary adjustment ensures that the margin between set and reset states is sufficiently widened before data is stored, thereby improving data storage reliability without affecting the basic write function.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the threshold voltage of memory cells based on their specific reliability requirements. By changing the threshold voltage parameter through controlled write operations with specific voltage levels and durations, the system optimizes the margin between set and reset states for each memory cell individually, resolving the contradiction between general write operations and high-reliability requirements.
2Reliability
If the threshold voltage of memory cells is increased to widen the margin between set and reset states, then data reliability improves, but the operating time and complexity of write operations increase
Solution Approach 1:
The patent applies local quality by selectively applying the threshold voltage adjustment process only to memory cells that require high reliability, rather than uniformly processing all memory cells. The row decoder and column decoder identify specific memory cells needing enhanced reliability and apply additional write operations only to those cells, thereby widening the margin for critical cells without unnecessarily extending the write time for all memory cells in the array.
Solution Approach 2:
The patent uses partial action by performing write operations with excessive voltage or duration only when necessary for high-reliability memory cells. The system determines whether a memory cell requires the enhanced threshold voltage adjustment based on its specific application requirements, applying the additional write operation only partially to selected cells rather than to the entire memory array, thus minimizing the overall time penalty.
3Manufacturing precision
If bias voltages are applied to word lines and bit lines to adjust threshold voltage, then the margin between states increases, but the device complexity and control circuit requirements increase
Solution Approach 1:
The patent applies universality by using the existing row decoder and column decoder circuits to perform multiple functions: normal address decoding, selection of high-reliability memory cells, and control of bias voltage application for threshold voltage adjustment. By making these existing decoders multi-functional, the patent achieves precise threshold voltage control without adding separate dedicated control circuits, thereby minimizing the increase in device complexity while maintaining high manufacturing precision.
Solution Approach 2:
The system uses self-service by allowing the row decoder and column decoder to automatically determine which memory cells require high-reliability treatment and to self-coordinate the application of bias voltages. The decoders utilize their inherent addressing and selection capabilities to identify target memory cells and control the write operation parameters without requiring external intervention or additional complex control logic, thereby reducing overall system complexity.
Data Source
AI summary
A semiconductor device may include a memory cell array including a plurality of memory cells arranged at locations where a plurality of word lines intersect with a plurality of bit lines, a row decoder configured to drive the plurality of word lines and a column decoder configured to drive the plurality of bit lines, wherein each of the plurality of memory cells has a set state or a reset state according to a normal write operation performed thereon, the plurality of memory cells include first memory cells in a specific area of the memory cell array, and the row decoder and the column decoder control a bit line and a word line coupled to a corresponding one of the first memory cells to increase a margin between the set state and the reset state of the corresponding first memory cell.