Memory Device Program-State Skipping for Faster Multi-Pass Programming
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Solution Overview
Problem
Non-volatile memory devices, such as NAND Flash memory, face increased program time due to multi-pass program operations, which involve multiple cycles of applying program and verify pulses, leading to prolonged operation times.
Innovation Solution
A program scheme is introduced that dynamically skips a set of program states in the first program pass, inhibiting the programming of a subset of memory cells associated with skipped program states, allowing only a second subset to be programmed, followed by a second pass to complete programming of all cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-pass program operations are performed to program all memory cells, then programming completeness is improved, but program time increases
Solution Approach 1:
The patent segments the memory cells into multiple subsets based on their target program states. In the first program pass, only a first subset of memory cells corresponding to a first set of program states is programmed, while a second subset corresponding to a second set of program states is skipped. In the second program pass, both subsets are programmed. This segmentation allows the patent to reduce the number of cycles in the first pass while ensuring all cells are eventually programmed, thus resolving the contradiction between programming completeness and program time.
Solution Approach 2:
The patent performs preliminary classification of memory cells into different subsets based on their target program states before the programming operation. This preliminary action enables the controller to strategically select which subset to program in the first pass and which to skip, optimizing the overall programming process while maintaining completeness through a subsequent second pass.
2Loss of time
If all memory cells are programmed in the first program pass, then program time is reduced, but the complexity of controlling program states increases
Solution Approach 1:
The patent divides memory cells into multiple subsets based on their target program states, which simplifies the control process. The controller only needs to manage a subset at a time during the first pass, reducing the complexity of controlling program states. The segmentation is implemented through bit line inhibition mechanisms that selectively enable or disable programming for specific subsets.
Solution Approach 2:
The patent applies different control strategies to different subsets of memory cells. In the first program pass, the first subset is programmed while the second subset is inhibited through bit line voltage control. This local differentiation allows the patent to simplify the overall control complexity by handling subsets independently with standardized control sequences.
3Productivity
If a single pass programs all memory cells, then programming speed increases, but the ability to optimize for different program states is reduced
Solution Approach 1:
The patent segments memory cells into multiple subsets based on their target program states, enabling optimized programming for different states. The first subset corresponds to a first set of program states and the second subset corresponds to a second set of program states. This segmentation allows the patent to apply state-specific programming optimizations in subsequent passes while maintaining high speed through efficient first-pass programming of the first subset.
Solution Approach 2:
The patent dynamically adjusts the programming strategy based on the target program states of different memory cell subsets. The controller adaptively selects which subset to program in each pass based on the specific program state requirements, enabling optimization for different program states while maintaining high programming speed through efficient multi-pass operations.
Data Source
AI summary
In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to perform a first program pass on the memory cells by skipping a programming on a first subset of the memory cells corresponding to a set of skipped program states. A target program state of each memory cell in the first subset is one of the set of skipped program states. The peripheral circuit is further configured to perform a second program pass on the memory cells.