Memory Source Line Segmentation for Low-Leakage Writes
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Solution Overview
Problem
Existing memory devices with floating gates experience undesirable leakage currents during write operations due to the biasing of source lines to ground voltage, which affects unselected memory cells, leading to inefficiencies and potential disturbances.
Innovation Solution
Implementing on-die circuitry within the memory device to bias source lines with digit lines during write operations using clamp and ground memory cells, eliminating the need to bring source lines out of the memory block, thereby reducing leakage currents and maintaining operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source lines are biased to ground voltage during write operations, then memory cells can be programmed, but leakage currents occur that affect unselected memory cells
Solution Approach 1:
The source line is divided into multiple independently controllable segments, with each segment serving a specific block of memory cells. This allows selective biasing of source line segments during write operations, enabling the selected segment to be coupled to the digit line while other segments remain at ground potential, thereby preventing leakage currents in unselected memory cells while maintaining write operation efficiency
Solution Approach 2:
The source line configuration transitions from a static ground-biased state to a dynamic state where individual source line segments can be selectively coupled to digit lines during write operations. This dynamic reconfiguration allows the memory device to adapt the source line biasing to the specific write operation being performed, eliminating leakage currents while maintaining programming capability
2Ease of operation
If source lines are brought out of the memory block for external biasing, then source line voltage control is improved, but device complexity increases
Solution Approach 1:
The memory device incorporates on-die circuitry that automatically manages source line biasing and coupling operations. The source line segments are self-configured to be coupled with digit lines during write operations through internal control logic, eliminating the need for external biasing circuitry while maintaining precise voltage control and reducing overall device complexity
Data Source
AI summary
Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.