Sense Amplifier Circuit Using Capacitive Voltage-Difference Amplification

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing sense amplifier circuits struggle to effectively detect small data line voltage differences due to intrinsic offset voltages, leading to reduced sensing accuracy and speed margins.

Innovation Solution

A sense amplifier circuit design that includes capacitive devices coupled between data lines and differential input terminals, with switching devices configured to charge these capacitors to data line voltages and then couple them to a reference voltage node, amplifying the voltage difference input to the sense amplifier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional sense amplifier circuits directly detect data line voltage differences, then the circuit structure remains simple, but sensing accuracy deteriorates when voltage differences are small relative to intrinsic offset voltages

Engineering Contradiction:
Improvesensing accuracyVSAvoidcircuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces capacitive devices as intermediary elements between the data lines and the sense amplifier input terminals. These capacitors are charged to data line voltages and then coupled to the sense amplifier, serving as a mediator that transforms small voltage differences into larger voltage swings that can be reliably detected despite intrinsic offset voltages in the sense amplifier circuitry.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The capacitive devices are pre-charged to the data line voltages before being coupled to the sense amplifier input terminals. This preliminary charging action stores the voltage difference information in the capacitors, which is then transferred to the sense amplifier in a controlled manner, enabling accurate detection of small voltage differences that would otherwise be lost in the intrinsic offset voltages.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If sense amplifiers directly amplify small voltage differences, then speed margins improve, but intrinsic offset voltages reduce sensing accuracy

Engineering Contradiction:
Improvespeed marginsVSAvoidsensing accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The capacitive devices act as intermediaries that decouple the small voltage difference detection from the sense amplifier's intrinsic offset voltages. By charging the capacitors to data line voltages and then coupling them to the sense amplifier, the system achieves both fast response (improved speed margins) and accurate detection (maintained sensing accuracy) because the voltage transformation occurs in the capacitive network rather than directly in the sense amplifier.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves sensing accuracy and speed margins by amplifying small data line voltage differences, particularly when intrinsic sense amplifier offset voltages are significant.

Implementation Method 1

capacitive devices coupled between a data line pair and differential input terminals of a voltage sense amplifier. The circuit includes switching devices configured to charge each of the capacitive devices to a voltage difference on the data lines

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12354701B2Sense amplifier circuit and method
Publication Date: 2025.07.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12354701B2 patent drawing
  • US12354701B2 patent drawing
  • US12354701B2 patent drawing

AI summary

A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.