NAND Flash Erase Voltage and Verify Scheduling Across Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in erase operations, particularly in NAND flash memory, due to the prolonged processing times and potential suspensions of erase operations, which can hinder the execution of other operations like write or read operations, and the need for improved processing capabilities.
Innovation Solution
A memory system with a memory controller that independently manages erase voltage application and erase verify operations, allowing for simultaneous execution on multiple blocks or planes, and adjusts erase voltage intensity based on previous operation outcomes to optimize efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are performed sequentially on multiple blocks, then each block receives complete erase voltage application and verify operations, but the overall processing time increases and other operations (write/read) are suspended
Solution Approach 1:
The patent segments the erase operation into two independent sub-operations: erase voltage application operation and erase verify operation. This segmentation allows the memory controller to manage and execute these operations independently on multiple blocks simultaneously, improving overall processing capability while ensuring each block receives complete treatment.
Solution Approach 2:
The patent introduces a new dimension of parallel execution by allowing erase voltage application and erase verify operations to occur concurrently on different blocks. This dimensional change from sequential to parallel processing enables multiple operations to proceed simultaneously without compromising reliability.
2Reliability
If erase voltage application time is extended to ensure complete erasure, then erasure reliability improves, but the operation duration increases and suspends other memory operations
Solution Approach 1:
By dividing the erase operation into separate voltage application and verify phases, the system can apply erase voltage to multiple blocks simultaneously without needing to wait for verify completion on each block, reducing total operation time while maintaining erasure reliability.
Solution Approach 2:
The erase voltage application operation is performed as a preliminary action on multiple blocks before verify operations are completed. This allows the system to prepare multiple blocks for erasure in advance, reducing the overall time loss and minimizing suspensions of other operations.
3Productivity
If the memory controller manages erase operations for multiple blocks independently, then processing capability and efficiency improve, but the device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle both erase voltage application and erase verify operations independently and simultaneously. This universal design enables the controller to manage multiple blocks efficiently without requiring separate dedicated controllers for each operation type.
Solution Approach 2:
The memory controller autonomously manages the segmentation and coordination of erase operations without external intervention. It automatically tracks which blocks have completed voltage application and which are awaiting verify, reducing the need for complex external management while improving processing capability.
Data Source
AI summary
According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.