Memory Array DAC Using Subthreshold Access Transistors
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Solution Overview
Problem
Existing memory devices require separate digital-to-analog converter (DAC) circuits for data conversion, leading to increased power consumption, chip area, and complexity, and are susceptible to inaccuracies due to temperature variations and data disturb during digital-to-analog conversion (DAC) operations.
Innovation Solution
A memory device configuration that utilizes the subthreshold region of access transistors in memory cells for DAC operations without separate DAC circuits, incorporating a temperature sensor to adjust gate voltages based on temperature and performs data conversion in a dedicated DAC region to avoid data disturb, thereby simplifying the design and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate DAC circuits are used for data conversion, then data conversion functionality is achieved, but power consumption increases
Solution Approach 1:
The patent merges the DAC functionality with the existing memory array structure by utilizing the access transistors and bit lines of the memory cells to perform digital-to-analog conversion. This integration eliminates the need for separate DAC circuits, thereby reducing power consumption and device complexity while maintaining the data conversion functionality.
Solution Approach 2:
The memory array is designed to serve multiple functions: data storage and digital-to-analog conversion. By making the memory structure universal, it can perform both traditional memory operations and DAC operations using the same hardware resources, thus eliminating dedicated DAC circuits and reducing overall system complexity.
2Area of stationary object
If separate DAC circuits are used for data conversion, then data conversion functionality is achieved, but chip area increases
Solution Approach 1:
The patent combines the DAC functionality with the memory array structure, using the same transistors and interconnects for both memory operations and data conversion. This merging eliminates the need for separate DAC circuit blocks, thereby reducing chip area and circuit complexity simultaneously.
Solution Approach 2:
The memory structure is designed to be multi-functional, serving as both storage and conversion hardware. This universality allows the system to perform DAC operations without adding dedicated conversion circuits, thus saving chip area and reducing overall circuit complexity.
3Device complexity
If separate DAC circuits are used for data conversion, then data conversion functionality is achieved, but device complexity increases
Solution Approach 1:
The patent integrates DAC functionality into the memory array, using the access transistors and bit lines for both memory access and data conversion. This integration simplifies the overall circuit architecture by eliminating separate DAC blocks, thereby reducing device complexity while maintaining conversion accuracy through careful design of the shared resources.
4Device complexity
If DAC operations are performed in the same region as data storage, then circuit simplification is achieved, but data disturb occurs
Solution Approach 1:
The patent divides the memory array into distinct regions: a first region dedicated to data storage and a second region dedicated to DAC operations. This segmentation allows DAC operations to be performed in the second region without causing data disturb in the first region, while still maintaining circuit simplification through the unified memory array structure.
Solution Approach 2:
Different regions of the memory array are assigned different functions with appropriate local characteristics. The first region is optimized for data storage with protected access, while the second region is configured for DAC operations. This local differentiation ensures data integrity in the storage region while enabling conversion functionality in the dedicated DAC region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption, chip area, and complexity by eliminating separate DAC circuits while maintaining accuracy through temperature-compensated gate voltage adjustments, and prevents data disturb by copying data to a dedicated DAC region for conversion.
Implementation Method 1
incorporating a temperature sensor to adjust gate voltages based on temperature
Implementation Method 2
utilizes the subthreshold region of access transistors in memory cells for DAC operations
Data Source
AI summary
A memory device includes a plurality of word lines, a bit line, a memory array, a control circuit, and a current summation circuit. The memory array includes a plurality of memory cells coupled to the bit line. Each of the plurality of memory cells includes an access transistor coupled to a corresponding word line among the plurality of word lines. The control circuit is configured to supply, correspondingly through the plurality of word lines, a plurality of word line voltages, different from each other, to the access transistors. The current summation circuit is configured to be coupled to the bit line, and to detect a bit line current on the bit line.