3D NAND Memory Node Integration Without DRAM Buffering
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Solution Overview
Problem
Existing data processing devices face challenges in reducing circuit area and power consumption due to the use of separate cache and NAND memory devices, which increase circuit area and power consumption through bus line connections.
Innovation Solution
The integration of a processor and memory with metal oxide transistors in a channel formation region, eliminating the need for a DRAM connection and incorporating a three-dimensional NAND memory device, reduces circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate cache and NAND memory devices are used, then data processing speed is improved, but circuit area and power consumption increase due to bus line connections
Solution Approach 1:
The patent combines the cache memory and NAND memory device into a single integrated memory structure, eliminating the need for separate bus line connections between discrete components. This merging reduces the overall circuit area while maintaining the data processing speed benefits of having both cache and NAND memory functionality present
2Speed
If separate cache and NAND memory devices are used, then data processing speed is improved, but power consumption increases due to bus line connections
Solution Approach 1:
The integrated memory structure consolidates cache and NAND memory operations within a single device, eliminating the power consumption associated with signal transmission over bus lines between separate components. This reduces overall power consumption while preserving the high-speed data processing capabilities
3Productivity
If DRAM connection is used, then data buffering is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent implements a unified memory structure where the NAND memory device performs multiple functions including data buffering, caching, and permanent storage. This multi-functionality eliminates the need for separate DRAM components dedicated to buffering, thereby reducing circuit area while maintaining data buffering capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a computer system with reduced circuit area and low power consumption, enabling efficient data processing with a novel operating method.
Implementation Method 1
A memory circuit capable of retaining data even when power is off, which takes advantage of a feature of an extremely low off-state current of a transistor including an oxide semiconductor (also referred to as Oxide Semiconductor or simply OS) in its channel formation region
Data Source
AI summary
A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.