3D NAND Partial Block Erase via Select Gate Control
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Solution Overview
Problem
As semiconductor memory technologies advance, challenges arise in maintaining efficient memory operations due to increased variability in memory cell characteristics over process, voltage, and temperature variations, particularly in scaling non-volatile memory devices like NAND flash, which leads to inefficiencies in erase operations and power consumption.
Innovation Solution
The implementation of a partial block erase operation in a memory system, where specific sets of vertical NAND strings are connected to shared word lines with physical shorts, allowing for individual control of drain-side select gates to selectively erase memory cells connected to certain word line fingers or strings, reducing the need to erase entire memory blocks for small data writes, and utilizing crystalline silicon channels to minimize erase disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a full block erase operation is performed on NAND flash memory, then all memory cells in the block are erased, but power consumption increases and unnecessary erase operations occur when only small data writes are needed
Solution Approach 1:
The patent divides the memory block into multiple independently controllable sub-blocks or regions by implementing separate select gate control for different NAND string sets. This allows selective erasure of only the necessary portion of the memory block rather than erasing the entire block, thereby reducing power consumption and improving erase operation efficiency when only small data writes are needed.
Solution Approach 2:
The patent enables partial block erase operations where only a subset of memory cells within a block are erased based on the actual data write requirements. This partial action principle avoids the excessive erasure of entire blocks when only small portions need to be written, directly addressing the power consumption issue while maintaining productivity.
2Quantity of substance
If process geometries are shrunk to scale down non-volatile memory devices, then cost per bit is reduced, but variability in memory cell characteristics increases
Solution Approach 1:
The patent implements different control mechanisms for different regions of the memory array, allowing localized optimization of erase operations. By applying selective erase control to specific NAND string sets while protecting others, the system can accommodate process variability in different regions and maintain reliable operation across the scaled memory device.
3Reliability
If entire memory blocks are erased for small data writes, then data integrity is maintained, but power consumption increases and programming speed decreases
Solution Approach 1:
The patent segments the memory block into independently controllable regions with separate select gate control, enabling selective erasure of only the necessary portion while preserving other regions. This maintains data integrity in the preserved regions while avoiding unnecessary power consumption from erasing the entire block for small data writes.
4Device complexity
If conventional erase operations are used on scaled memory devices, then simplicity is maintained, but erase disturb increases due to carrier generation
Solution Approach 1:
The patent modifies the erase operation parameters by implementing selective voltage application to different select gates for different NAND string sets. This parameter change allows control over carrier generation and distribution, reducing erase disturb in non-target regions while maintaining the relatively simple erase operation structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power efficiency and memory performance by allowing partial block erases, reducing unnecessary power consumption and improving programming speed, while minimizing erase disturb through reduced carrier generation rates in crystalline silicon channels.
Implementation Method 1
minimizing erase disturb through reduced carrier generation rates in crystalline silicon channels
Data Source
AI summary
Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.