3D NAND Memory Pillar Stack for Lower Connection Complexity

The patent divides the three-dimensional stack into modular units consisting of alternating interconnect layers and insulating layers. Each layer is segmented and assigned a specific function: interconnect layers for electrical connections and insulating layers for isolation. This segmentation allows complex three-dimensional structures to be built from simpler, standardized modules, reducing overall structural complexity while maintaining high storage capacity.

The patent implements a nested structure where memory pillars are formed within the stacked layers, with each pillar containing multiple memory cell transistors arranged in series. The members extend through multiple interconnect layers, creating a nested configuration where smaller functional units are integrated within larger structures. This nesting approach enables high storage capacity within a compact three-dimensional footprint while organizing complexity hierarchically.

The patent forms members that extend through multiple interconnect layers using preliminary actions performed during the layer-by-layer construction process. The members are formed to protrude from upper surfaces of insulating layers before subsequent interconnect layers are deposited. This preliminary formation allows the members to be positioned and sized correctly in advance, simplifying later steps for connecting memory cell transistors across multiple layers and reducing manufacturing complexity.

The insulating layers serve as intermediaries between interconnect layers, providing a stable platform for forming members. The members extend through the insulating layers, which act as mediators that isolate electrical signals while allowing mechanical connection. This intermediary structure enables reliable connectivity across layers without requiring direct contact between conductive elements, simplifying the manufacturing process while maintaining electrical isolation.