3D NAND Program Disturbance via Dynamic String Selection Voltage Control
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Solution Overview
Problem
Three-dimensional flash memory devices face challenges in data reliability due to program disturbance and interference coupling between cells during programming operations, especially when storing multiple bits per memory cell.
Innovation Solution
A nonvolatile memory device and program method that adjusts voltages using a program voltage manager, applying bit line program voltage and changing turn-on voltages to turn-off voltages during different stages of the program operation to minimize data reliability decreases, with specific voltage conditions applied to bit lines and string selection lines to prevent program disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional flash memory structure is used to increase degree of integration, then storage capacity is improved, but data reliability deteriorates due to program disturbance and interference coupling between cells
Solution Approach 1:
The patent applies different voltage conditions to different string selection lines based on their selection state. Selected string selection lines receive turn-on voltages to enable programming, while unselected string selection lines receive turn-off voltages to prevent program disturbance. This local differentiation of voltage conditions resolves the contradiction by allowing high storage capacity through 3D structure while maintaining data reliability through targeted voltage control.
Solution Approach 2:
The patent dynamically changes voltage parameters during the program operation. The voltage on unselected string selection lines is changed from turn-on voltage to turn-off voltage during the bit line setup section to prevent interference. This parameter change approach allows the system to achieve both high integration and data reliability by adapting voltage conditions to the specific operational phase and string selection state.
2Quantity of substance
If multiple bits are stored at a memory cell to increase storage density, then storage capacity is improved, but data reliability deteriorates due to increased program disturbance and interference coupling
Solution Approach 1:
The patent implements local quality control by applying turn-off voltages specifically to unselected string selection lines during programming operations. This localized voltage control prevents program disturbance from affecting adjacent memory cells, thereby maintaining data reliability even when multiple bits are stored per cell through multi-bit cell architectures.
Solution Approach 2:
The patent applies preliminary anti-action by setting unselected string selection lines to turn-off voltage conditions before programming operations begin. This preliminary voltage configuration prevents potential program disturbance and interference coupling before they can occur, protecting the reliability of multi-bit stored data.
3Productivity
If conventional voltage application is used during program operation, then program speed is maintained, but program disturbance occurs causing data reliability to decrease
Solution Approach 1:
The patent performs preliminary action by changing the voltage of unselected string selection lines to turn-off voltages during the bit line setup section, before the actual programming pulse is applied. This preliminary voltage adjustment prevents program disturbance without delaying the programming operation, thereby maintaining program speed while improving data reliability.
Solution Approach 2:
The patent implements dynamic voltage control where the voltage on unselected string selection lines is changed from turn-on to turn-off during different sections of the program operation. This dynamic adjustment allows the system to maintain fast program speeds while preventing program disturbance through real-time voltage adaptation.
Data Source
AI summary
A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage.