Read-Only Memories TRIZ Cases

A training circuit executes input calibration concurrently with memory core operations to reduce latency.

Dual memory arrays perform out-of-phase operations to maintain continuous data availability during computation.

A selective erase method precharges and boosts the channel of a selected memory cell to enable targeted data clearance.

A memory device uses row counters and flags to queue addresses for targeted refresh operations.

Segmented amplifier sections accelerate reference current rise times, reducing multivalued memory cell determination delays.

A PMIC supplies periodic power directly to storage devices without activating the vehicle system, preventing data loss from battery drain.

Reusing the erased flag for copy tracking eliminates additional writes, preserving Partial Page Programming availability in MLC NAND devices.

Dynamic adjustment of write voltage parameters via rewrite counters prevents over-programming in deteriorated NAND flash memory cells.

Making unselected sub-block drain-end select gates temporarily conductive reduces capacitive coupling and hot electron injection during read operations.

A negative gate stress scheme removes shallowly-trapped charges during multi-pass programming to narrow threshold voltage distributions.

A NAND flash memory device receives command and address signals at a first frequency while processing data signals at a higher second frequency.

Segmented bit lines isolate high write voltages from read paths, preventing unintended breakdown of non-selected anti-fuse elements.

Segmented gate structures with intermediate electrodes reduce program/erase power below 5 volts through field-dependent resistivity modulation.

Segmented shadow-programming sequences reduce word line coupling effects during multi-level cell threshold voltage adjustments.

Solid state memory controllers adjust decoding parameters during read retries to resolve latency bottlenecks caused by repeated error correction failures.

Segmenting the array allows longer refresh cycles, reducing power consumption while maintaining data retention.

A sense amplifier node TDC amplifies voltage differences to digitize data without latch circuit control.

Intermixes read operations on adjacent memory cells to apply voltage compensation, reducing floating gate coupling errors in multi-state flash devices.

Dynamic ramped inhibit voltage waveforms balance program and inhibit disturb by compensating leakage effects through time-varying potentials.

Counter-transitioning waveforms on neighboring word lines reduce capacitive coupling during non-volatile memory programming.

A nonvolatile memory system identifies dummy wordlines via threshold voltage states to skip unnecessary error correction.

Detecting fabrication misalignments in memory arrays to adjust read verify timing parameters for optimal performance.

A program verify circuit compares digital counts with target voltages to control memory cell programming.

Pre-calculated trim values eliminate repetitive read-modify-write cycles, accelerating updates and reducing wear on memory devices.

A semiconductor memory device maintains specific voltage differences between wirings during erase operations.

A device selection circuit generates localized chip enable signals using unused ONFI protocol states.

Simultaneous column programming narrows threshold voltage distributions in SONOS memory cells.

Selective bit scanning reduces unnecessary programming cycles, lowering power consumption while maintaining NOR flash memory reliability.

Simultaneous latch setting reduces program verification cycles and power consumption in nonvolatile memory devices.

A semiconductor memory device detects conductive layer leak current during access operations to identify faulty blocks.

A shift wrapper reroutes signals between block inputs and redundant cell lines to bypass defective memory elements.

An open-loop current generator creates a monotone biasing voltage pattern, reducing chip area waste and increasing reading speed in multi-level memory devices.

Pre-programmed operating parameters in ROM allow post-shipment selection, resolving fixed parameter limitations during cell deterioration.

A memory controller uses shift read and threshold voltage comparison to identify error causes in NAND flash.

A memory read circuit uses combined P-type and N-type pre-charge transistors to control the read bit line voltage level.

Multiple sense operations stabilize marginal memory element states and correct noise-induced errors, ensuring accurate data retrieval.

A memory chip uses control logic to generate pseudo-data, enabling flexible programming of memory units with varying bit capacities.

Current supply circuit changes memory cell resistance state via controlled current flow to enable fast write operations.

Two-pass programming technique coarsely programs memory cell threshold voltages to reduce programming time while maintaining precision.

A one-time programmable latch circuit uses a single gate oxide antifuse device to store logic values in nonvolatile memory.

A non-volatile memory switch routes multi-host transactions using host identifier logic to present a single root complex.

Controller omits temperature compensation for buffer writes in segmented memory regions to accelerate programming speed.

An SSD controller uses integrated voltage monitoring to dynamically limit concurrent flash memory operations.

A semiconductor memory device applies bias voltages to dummy bit lines to minimize standby current consumption.

A nonvolatile memory controller adjusts program step voltage to reduce programming pulses and extend NAND flash lifespan.

A semiconductor device trims power supply voltages using an internal reference voltage generation circuit.

An adaptive data bus inversion circuit selects partial or full bit inversions to minimize transitions during high-speed memory transfers.

Dynamic voltage control on unselected string selection lines reduces program disturbance in stacked memory cells, maintaining data reliability.

Voltage detection enables subgroup programming to reduce time and prevent cell degradation in high VCC environments.

A dummy repair logic unit mirrors the delay path of a repair address decision to generate a synchronized control signal for word line activation.