3D Memory Read Disturb Reduction via SGD Conductive Control

The patent applies preliminary anti-action by making SGD transistors conductive BEFORE the hot electron injection can occur. The method ramps up unselected word line voltages while SGD transistors are in the conductive state, which prevents the formation of channel gradients that would otherwise cause hot electron injection. By establishing the protective conductive state in advance, the harmful injection effect is prevented before it can damage memory cells.

The patent utilizes parameter changes by dynamically adjusting the electrical state of SGD transistors during the read operation. The transistors are switched from non-conductive to conductive states by controlling their gate voltages, and this parameter change is timed to coincide with the ramping of unselected word line voltages. This dynamic parameter adjustment enables the system to prevent hot electron injection while maintaining proper read operation conditions.

The patent applies segmentation by dividing the memory block into selected and unselected sub-blocks, and further segmenting the control of SGD transistors by sub-block. Instead of uniformly controlling all SGD transistors, the method selectively makes SGD transistors in unselected sub-blocks conductive during specific phases of the read operation. This segmented control approach allows the system to maintain simplicity in selected sub-blocks while actively protecting unselected sub-blocks from capacitive coupling disturbances.

The patent implements local quality by applying different electrical conditions to different regions of the memory block. Specifically, SGD transistors in unselected sub-blocks are made conductive during the voltage ramp-up phase to locally protect those specific regions from capacitive coupling, while other regions maintain their normal operation conditions. This localized quality adjustment enables targeted protection without affecting the overall simplicity of the read operation.

The patent applies preliminary action by preparing the SGD transistor conductive state before the full read pass voltage is applied to unselected word lines. By establishing the conductive path through SGD transistors in advance, the system prevents channel gradient formation that would occur if voltage were applied without this preparatory step. This preliminary action maintains fast read speeds while preventing the harmful effects of channel gradients.

The patent uses SGD transistors as intermediary elements between the word lines and the memory cell channels. These intermediary transistors are controlled to be conductive during the voltage ramp-up phase, acting as a buffer that prevents direct formation of harmful channel gradients. The intermediary SGD transistors mediate the voltage application process, allowing fast reads while protecting the memory cells from hot electron injection.