Selective ECC Function for DRAM Refresh Current Reduction
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face increased refresh current and power consumption as memory capacitance increases, necessitating a method to reduce refresh operations without compromising data retention.
Innovation Solution
Implementing a selective ECC function that divides memory cells into blocks based on data retention characteristics, using ECC cells to repair fail cells in one block and redundancy cells in another, allowing for longer refresh cycles while maintaining data stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacitance increases to improve storage capacity, then the data retention capability is improved, but the refresh current and refresh power increase
Solution Approach 1:
The memory cell array is divided into multiple blocks, with certain blocks designated as ECC select blocks that undergo ECC operations while other blocks undergo redundancy cell repairs. This segmentation allows different refresh strategies to be applied to different regions, reducing the overall refresh current requirement compared to uniform refresh of the entire array.
Solution Approach 2:
Different repair methods are applied to different blocks based on their specific characteristics. ECC operations are applied selectively to blocks where they are most effective, while redundancy cell repairs are used in other blocks. This localized approach optimizes the balance between data retention and power consumption.
2Use of energy by moving object
If the refresh cycle is extended to reduce refresh frequency, then the refresh power consumption is reduced, but the data retention reliability deteriorates
Solution Approach 1:
ECC operations are performed in advance on data before it is stored in the memory cell array. This preliminary error correction ensures that even if the refresh cycle is extended, the data can be reliably recovered or corrected, maintaining data retention reliability while allowing longer refresh intervals.
Solution Approach 2:
ECC cells and redundancy cells act as intermediary structures that protect the main memory data. These intermediary elements provide an additional layer of protection that allows the system to tolerate longer refresh cycles without compromising data integrity.
3Reliability
If ECC operations are applied to all blocks to improve error correction capability, then the data reliability is improved, but the device complexity and overhead increase
Solution Approach 1:
The memory array is segmented into ECC select blocks and non-ECC blocks. By applying ECC operations only to specific blocks rather than the entire array, the patent reduces the overhead and complexity associated with ECC implementation while maintaining error correction capability where most needed.
Solution Approach 2:
Instead of applying ECC operations to all blocks (excessive action), the patent applies them only to specific blocks where they provide the most benefit (partial action). This selective application reduces the overall complexity and overhead while still achieving the desired reliability improvement.
Data Source
AI summary
A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device.