Memory Chip Pseudo-Data Programming for Storage Efficiency
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Solution Overview
Problem
3D NAND flash memory units at the ends of the Z direction have inferior component characteristics compared to those in the middle, leading to reduced reliability and inefficient use of space due to the need for multiple circuit configurations for different bit numbers.
Innovation Solution
A memory device with a memory controller and chip that configures data into sub-data and pseudo-data, allowing memory units to store up to N bits, with the control logic circuit programming threshold voltages within specific voltage ranges to accommodate varying bit lengths, thereby optimizing storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit configurations are used to correspond to different bit numbers in memory units, then programming flexibility is improved, but device complexity and space utilization deteriorate
Solution Approach 1:
The patent applies universality by designing a single circuit configuration that can handle multiple bit numbers (K bits where K < N) through the generation of pseudo-data. Instead of creating separate circuits for different bit configurations, one universal circuit uses the pseudo-data generation mechanism to adapt to various programming requirements, thereby reducing device complexity while maintaining programming flexibility.
Solution Approach 2:
The patent changes the parameter of data representation by generating pseudo-data to transform variable-bit programming into a fixed-N-bit processing framework. By modifying how data is prepared (adding pseudo-data bits) rather than changing the circuit architecture, the system achieves adaptability without increasing complexity.
2Reliability
If memory units at ends in Z direction store fewer bits, then reliability is improved, but storage efficiency deteriorates
Solution Approach 1:
The patent applies local quality by allowing different memory units to be programmed with different actual data bit lengths (K bits) while maintaining a uniform N-bit processing framework. Memory units at the ends can store fewer bits (lower K) to match their reliability characteristics, while middle units can store more bits, optimizing overall storage efficiency without compromising reliability.
Solution Approach 2:
The patent changes the parameter of stored data length from fixed N bits to variable K bits (where K < N) by introducing pseudo-data. This allows memory units with different reliability characteristics to store appropriate amounts of actual data while using the same physical structure and processing mechanism.
3Quantity of substance
If memory units store up to N bits of data, then storage capacity is improved, but programming complexity increases
Solution Approach 1:
The patent segments the N-bit data storage into K bits of actual data and (N-K) bits of pseudo-data. This segmentation allows the system to maintain high storage capacity (N bits per unit) while simplifying programming complexity by handling only K meaningful bits, with the remaining bits being automatically generated fillers.
Solution Approach 2:
The patent introduces pseudo-data as an intermediary element between the actual K-bit data and the N-bit storage requirement. This intermediary fills the gap without requiring complex programming logic, as the pseudo-data generation follows a predetermined pattern based on the actual data values.
Data Source
AI summary
A memory chip, a memory device and an operation method are disclosed. The memory chip includes a number of memory units and a control logic circuit. The memory units could be configured as TLC, MLC or SLC. The control logic circuit is configured to use TLC programming approach to program MLC and SLC.