Anti-fuse Memory Cell Write Disturb Prevention Circuit
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Solution Overview
Problem
Non-volatile semiconductor storage devices using anti-fuse elements with a MOS structure face issues of 'write disturb fault' due to high voltage requirements, which can break down other elements, and 'insufficient test coverage' as data cannot be erased, making it difficult to ensure reliable read and write operations.
Innovation Solution
A non-volatile semiconductor storage device design that includes a memory cell array with anti-fuse elements, transistors, and a write-disturb prevention circuit, which charges read bit lines to a certain voltage during write operations to prevent incorrect writes, and a test read function to ensure data can be read before writing, improving reliability and test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to break down the anti-fuse element for data write operation, then data can be written to the memory cell, but other elements in the same device may also break down causing write disturb fault
Solution Approach 1:
The patent divides the bit line into two separate lines: a read bit line and a write bit line. This segmentation allows independent voltage control for read and write operations. During write operation, the write bit line can be charged to high voltage while the read bit line remains at low voltage, preventing unintended breakdown of anti-fuse elements connected to the read bit line.
Solution Approach 2:
The patent applies different voltage levels to different parts of the system locally. The write bit line is charged to high voltage (VHH) only when write operation is performed, while the read bit line maintains low voltage. This local voltage differentiation ensures that high voltage is applied only where needed (write bit line) and not to other sensitive elements (read bit line).
2Ease of operation
If anti-fuse element with MOS structure is used for non-volatile storage, then simple voltage application for read/write operation is achieved, but tolerance for noise and leak current is low causing write disturb fault
Solution Approach 1:
The patent segments the bit line function into separate read and write bit lines. This allows the write bit line to be independently charged to high voltage without affecting the read bit line, thereby preventing noise and voltage fluctuations on the read bit line from causing unintended write operations to anti-fuse elements.
3Duration of action of stationary object
If anti-fuse element is used as irreversible non-volatile storage element, then data retention without power is achieved, but data cannot be erased making test coverage insufficient
Solution Approach 1:
The patent enables preliminary testing of read and write operations before actual data is written to the anti-fuse element. By allowing test operations on the memory cell structure (without permanent breakdown), the system can verify proper functioning of transistors, bit lines, and control circuits before committing to irreversible write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the reliability of non-volatile semiconductor storage devices by preventing write disturb faults and improving test coverage, ensuring accurate data storage and retrieval operations.
Implementation Method 1
a write-disturb prevention circuit for, in writing data, charging the read bit lines to a certain voltage
Data Source
AI summary
A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.