Device Selection Circuit for NAND Flash Pin Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash systems require a large number of costly chip enable lines for accessing multiple NAND flash chips, leading to excessive routing and pin-out requirements, which increases the cost and complexity of designs such as solid-state NAND flash drives.
Innovation Solution
Implementing a device selection circuit that utilizes an unused state of control signals (ALE and CLE) to provide localized chip enable signals, reducing the need for individual chip enable pins and allowing for a larger number of devices to be ganged without additional pins or extended lines, by using a selector circuit with a latch, control signal decoder, and drivers to assert chip enable signals within the existing ONFI protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate chip enable lines are used to access multiple NAND flash chips, then parallelism and overall performance are improved, but routing complexity and pin-out requirements increase significantly
Solution Approach 1:
The patent combines multiple chip enable control functions into a single shared chip enable line. Instead of having separate chip enable lines for each NAND flash chip, the system uses one common chip enable line that is controlled by a device selection circuit. This circuit decodes address signals to determine which chip should be enabled, merging multiple control functions into a single physical line while maintaining the ability to selectively access individual chips.
Solution Approach 2:
The patent introduces a device selection circuit as an intermediary between the controller and the NAND flash chips. This intermediary circuit receives the shared chip enable line and address signals, performs decoding logic, and generates individual enable signals for each chip. The intermediary absorbs the complexity of routing and pin-out requirements, allowing the main system to use fewer pins while maintaining full chip selection capability.
2Ease of operation
If multiple separate chip enable lines are used to access multiple NAND flash chips, then individual chip access capability is improved, but pin-out requirements and manufacturing cost increase
Solution Approach 1:
The patent merges multiple chip enable control functions into a single shared chip enable line. Instead of having separate chip enable lines for each NAND flash chip, the system uses one common chip enable line that is controlled by a device selection circuit. This circuit decodes address signals to determine which chip should be enabled, merging multiple control functions into a single physical line while maintaining the ability to selectively access individual chips.
Solution Approach 2:
The shared chip enable line serves multiple functions - it can enable any of the NAND flash chips in the system by combining with the address decoding logic. The single line is universally applicable to all chips, replacing the need for dedicated enable lines for each chip. This multi-functionality reduces the total number of pins required while maintaining full individual chip access capability.
3Quantity of substance
If more NAND flash chips are ganged together to increase memory space, then memory capacity is improved, but the number of required chip enable lines increases proportionally
Solution Approach 1:
The patent transitions from a one-to-one mapping between chip enable lines and chips to a many-to-one relationship. Instead of requiring N enable lines for N chips, the system uses a single enable line combined with address decoding in a different dimensional space (logical addressing space). The device selection circuit performs the mapping from logical address space to physical chip selection, allowing exponential scaling of memory capacity without linear scaling of pin requirements.
Solution Approach 2:
The patent introduces a device selection circuit as an intermediary between the controller and the NAND flash chips. This intermediary circuit receives the shared chip enable line and address signals, performs decoding logic, and generates individual enable signals for each chip. The intermediary absorbs the complexity of routing and pin-out requirements, allowing the main system to use fewer pins while maintaining full chip selection capability.
Data Source
AI summary
Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals).