Negative Gate Stress in Multi-Pass NAND Flash Programming
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Solution Overview
Problem
NAND Flash memory devices face issues with fast initial charge loss and degraded programming distributions due to shallowly-trapped charges, which affect the threshold voltage distribution and read window budget, and existing negative gate stress (NGS) operations are not suitable for all memory cells after verify operations.
Innovation Solution
A novel NGS scheme is implemented in multi-pass programming, enabling NGS operations on all memory cells in a selected row, including those that have passed the verify operation, to remove shallowly-trapped charges and narrow the threshold voltage distribution without reducing the read window budget, by applying a low voltage on DSGs and a high positive voltage on word lines, effectively boosting the string potential and enabling NGS operations on all memory cells in a non-last programming pass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If NGS operation is performed on memory cells that have passed verify operation, then shallowly-trapped charges are removed and threshold voltage distribution is narrowed, but read window budget is reduced
Solution Approach 1:
The patent applies different voltage conditions to different groups of memory cells based on their verify status. Memory cells that have passed verify operations receive a different voltage treatment (lower voltage on word line) compared to those that have not passed verify, allowing selective NGS operation that removes shallowly-trapped charges only from cells that need it, thereby narrowing threshold voltage distribution without adversely affecting cells that have already achieved desired voltage levels
Solution Approach 2:
The patent performs NGS operation as a preliminary step before the final verify operation in multi-pass programming. By removing shallowly-trapped charges in advance through NGS operation, the threshold voltage distribution is narrowed before the final verification, ensuring that only cells with stable charge states pass the verify, thus improving manufacturing precision without compromising read window budget
2Manufacturing precision
If NGS operation is performed between programming and verify operations, then shallowly-trapped charges are removed and programming distribution is improved, but additional operation time is required
Solution Approach 1:
The patent merges the NGS operation with the existing multi-pass programming structure by integrating it between the programming operation and verify operation within the same programming pass. This combination allows the NGS operation to be performed as part of the normal programming flow rather than as a separate additional step, improving programming distribution while minimizing additional time overhead
Solution Approach 2:
The patent implements NGS operation periodically at specific intervals during multi-pass programming, specifically between programming and verify operations in non-last programming passes. This periodic application of NGS operation ensures that shallowly-trapped charges are removed at optimal moments in the programming process, improving programming distribution while maintaining efficient timing by not applying NGS continuously
Data Source
AI summary
A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.