Memory Read Circuit P-N Pre-charge Transistor Voltage Control
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Solution Overview
Problem
Existing memory read circuits face inefficiencies in reading storage cells due to the strong pull-up strength of P-type pre-charge transistors, leading to noise margin concerns and increased access time, while N-type pre-charge transistors result in insufficient voltage levels in noisy environments, affecting storage cell density and performance.
Innovation Solution
A memory read circuit utilizing a combination of P-type and N-type pre-charge transistors, where one N-type transistor and two P-type transistors work together to control the read bit line voltage, balancing pull-up strength and reducing noise margin concerns by ensuring the voltage remains beneath the trip level for logic HI and efficiently rises above for logic LO.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If P-type pre-charge transistors are used, then the read bit line voltage rises efficiently above the trip level for logic LO, but the strong pull-up strength causes noise margin concerns and increases access time
Solution Approach 1:
The patent changes the electrical parameters of the pre-charge circuit by combining P-type and N-type transistors with different threshold voltages and drive strengths. The P-type transistor (Q3) provides strong pull-up capability while the N-type transistor (Q4) with its threshold voltage characteristic limits the maximum voltage to VCC-VT, thereby controlling the voltage swing parameters to simultaneously improve speed and maintain noise margin.
2Reliability
If N-type pre-charge transistors are used, then noise margin is improved by limiting voltage swing, but the voltage levels become insufficient in noisy environments
Solution Approach 1:
The patent merges P-type and N-type transistors in a complementary configuration where the P-type transistor Q3 attempts to pull the bit line to VCC while the N-type transistor Q4 limits it to VCC-VT. This combination allows the circuit to benefit from both the strong drive capability of P-type devices and the voltage limiting characteristic of N-type devices, ensuring sufficient voltage levels while maintaining noise margin.
3Productivity
If P-type pre-charge transistors are used, then read bit line voltage rises efficiently, but storage cell density is affected due to increased access time
Solution Approach 1:
By changing the voltage swing parameter from full VCC swing to a limited swing ending at VCC-VT through the N-type transistor's threshold voltage effect, the access time is reduced. This parameter change allows for faster read operations without requiring larger transistor sizes, thereby maintaining higher storage cell density while improving memory performance.
Data Source
AI summary
A memory is described. The memory includes a storage cell. The memory also includes a read bit line coupled to the storage cell. The memory also includes at least one N type pre charge transistor coupled between the read bit line and a power supply node. The at least one N type pre-charge transistor is to pre-charge the read bit line. The memory also includes at least one P type pre charge transistor that is also coupled between the read bit line and the power supply node. The at least one P type pre-charge transistor is to pre-charge the read bit line with the at least one N type transistor.