Selective Erase Method for NAND Flash Memory Cells
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Solution Overview
Problem
In NAND flash memory devices, the existing erase operation is performed on a memory-block basis, leading to increased time for data updates as all cells in a memory-block are erased even if only a portion is updated, which slows down the operating speed of nonvolatile memory devices.
Innovation Solution
A method and semiconductor memory device that selectively erase data by precharging the channel of a selected memory cell, boosting the channel voltage, and applying an erase voltage lower than the positive voltage to the selected word line, while using an erase inhibition voltage on unselected bit lines to prevent unwanted erasure of other cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is performed on a memory-block basis, then all cells in the memory-block are erased ensuring complete data clearance, but the time taken to update data in specific memory cells increases
Solution Approach 1:
The patent divides the memory block into multiple strings and further segments the erase operation to target specific strings or even individual memory cells within selected strings. Instead of erasing all memory cells in a memory block, the method applies erase voltage only to selected strings containing the memory cells that need updating, thereby segmenting the erase operation spatially and temporally to reduce overall erase time while maintaining data clearance completeness for the required cells
Solution Approach 2:
The patent applies different voltage conditions to different regions of the memory array. Selected bit lines receive an erase permission voltage that enables erasure, while unselected bit lines receive an erase inhibition voltage that prevents erasure. This local differentiation allows specific memory cells to be erased while preserving others in the same memory block, achieving selective erasure that reduces update time without compromising the reliability of data clearance for the intended cells
2Productivity
If selective erase of specific memory cells is implemented, then data update speed is improved, but the complexity of voltage control increases
Solution Approach 1:
The patent employs a dual-voltage control scheme where bit lines serve multiple functions: during erase operations, selected bit lines function as erase permission lines receiving erase permission voltage, while unselected bit lines function as erase inhibition lines receiving erase inhibition voltage. This multi-functional use of existing bit line infrastructure enables selective erasure without requiring entirely separate control circuits, thereby improving data update speed while limiting the increase in voltage control complexity
Solution Approach 2:
The patent applies preliminary voltage precharging to selected bit lines before the actual erase operation. By precharging selected bit lines to a first voltage level and unselected bit lines to a second voltage level in advance, the system prepares the voltage conditions necessary for selective erasure beforehand. This preliminary action simplifies the subsequent erase operation and reduces the overall complexity of real-time voltage control, thereby enabling faster data updates with manageable control complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster data updates by selectively erasing specific memory cells, improving the operating speed of nonvolatile memory devices without affecting unselected cells.
Implementation Method 1
boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string
Implementation Method 2
erasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell
Data Source
AI summary
A method of erasing a semiconductor memory device includes precharging a channel of a selected memory cell of a selected string including memory cells; boosting a channel of the selected string by supplying a positive voltage to word lines of the respective memory cells of the selected string; and erasing the selected memory cell by supplying an erase voltage lower than the positive voltage to a selected word line associated with the selected memory cell.