Dynamic Program Step Voltage Control for NAND Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of bits in NAND flash memory cells has narrowed the threshold voltage window, requiring numerous low-program step voltage pulses for programming, which increases programming time, reduces throughput, and negatively affects the lifespan of Solid State Drives (SSDs) due to higher Bit Error Rates (BER).
Innovation Solution
A nonvolatile memory controller that initially programs NAND flash memory cells using an initial program step voltage and dynamically adjusts it based on predetermined thresholds, such as program and erase cycles, error rates, or age, to reduce the number of programming pulses and extend the lifespan of NAND flash memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a fixed low program step voltage is used to achieve the limited threshold voltage window in TLC NAND flash memory devices, then the threshold voltage distribution is maintained, but the programming time increases and the throughput decreases
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed program step voltage to a dynamic, adjustable program step voltage that changes based on the NAND flash memory device's lifetime and wear level. The memory controller monitors device characteristics and adjusts the program step voltage accordingly, allowing the system to adapt its programming parameters to current device conditions rather than using a static voltage throughout the device's operational life.
Solution Approach 2:
The patent implements parameter changes by modifying the program step voltage parameter based on device lifetime and wear characteristics. The memory controller changes the program step voltage from an initial value to different values at different stages of the device's life, optimizing the balance between maintaining threshold voltage distribution and achieving acceptable programming speeds at each stage.
2Manufacturing precision
If numerous programming pulses are used to program memory cells with a fixed low program step voltage, then the threshold voltage window is maintained, but the Bit Error Rate increases and device lifespan decreases
Solution Approach 1:
The system dynamically adjusts the program step voltage based on the number of program/erase cycles and device wear level. As the device accumulates more cycles and shows signs of wear, the controller modifies the voltage parameters to reduce stress on the memory cells, thereby lowering the Bit Error Rate and extending device lifespan while still achieving the required threshold voltage window.
Solution Approach 2:
The memory controller implements feedback by monitoring device characteristics such as program/erase cycle counts and performance metrics, then using this information to adjust the program step voltage. This closed-loop approach allows the system to respond to actual device conditions and optimize programming parameters to minimize Bit Error Rate and maximize device longevity.
Data Source
AI summary
A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.