Ramped Inhibit Voltage for Memory Programming Disturb
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Solution Overview
Problem
Memory devices face a trade-off between program disturb (PD) and inhibit disturb (ID) due to the challenge of maintaining a sufficiently high inhibit voltage to reduce PD without increasing ID, as higher inhibit voltages can lead to unintended programming of inhibited cells.
Innovation Solution
Ramping up the inhibit voltage during the program operation improves the trade-off between PD and ID by maintaining an overall average inhibit voltage constant or reducing it, thereby reducing PD and ID, while compensating for leakage effects through a triangular or periodic inhibit voltage waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inhibit voltage is increased to reduce program disturb (PD), then PD is reduced, but inhibit disturb (ID) increases
Solution Approach 1:
The patent applies dynamics by transitioning from a static inhibit voltage to a dynamic ramped inhibit voltage waveform. The inhibit voltage starts at an initial level and increases over time during the program operation window, allowing the system to adapt the voltage level to different stages of the programming process. This dynamic approach enables reduced initial voltage (lowering ID) while achieving sufficient final voltage (reducing PD).
Solution Approach 2:
The patent changes the inhibit voltage parameter from a constant value to a time-varying ramped waveform. By modifying the voltage parameter dynamically during the program operation, the system optimizes both PD and ID performance. The ramped waveform parameters (initial voltage, final voltage, ramp duration) are adjusted to achieve the desired balance between reducing program disturb and minimizing inhibit disturb.
2Reliability
If a high inhibit voltage is applied to maintain low program disturb (PD), then PD is reduced, but the total number of disturbed cells increases due to higher ID
Solution Approach 1:
The dynamic ramped inhibit voltage waveform allows the system to apply lower voltage during early stages when ID is the primary concern, and gradually increase voltage as the program operation progresses and PD becomes the dominant concern. This temporal differentiation in voltage application reduces the cumulative number of disturbed cells while maintaining program reliability.
Solution Approach 2:
The ramped inhibit voltage can be implemented as a periodic or staged voltage application, where the voltage increases in controlled steps or continuous ramps during the program operation window. This periodic modulation of the inhibit voltage enables optimization of both PD and ID across different time periods of the programming process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the total number of disturbed cells by maintaining a higher average boosted channel potential and controlling ID, achieving better performance in minimizing both PD and ID.
Implementation Method 1
allowing the channel to capacitively couple to the inhibit voltage
Implementation Method 2
compensating for leakage effects through a triangular or periodic inhibit voltage waveform
Data Source
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AI summary
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.