Adaptive Data Bus Inversion Circuit for SSO Noise Reduction
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Solution Overview
Problem
Existing memory device interfaces face challenges in reducing Simultaneous Switching Output (SSO) noise and power consumption while maintaining high switching speeds, particularly due to the limitations of traditional data bus inversion schemes.
Innovation Solution
The implementation of an adaptive Data Bus Inversion (DBI) scheme that compares data words and their inverses with prior data words, as well as partially-inverted options, to select the configuration resulting in fewer flipped bits, thereby reducing SSO noise and power consumption, and uses additional bits to indicate the inversion conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional data bus inversion schemes are used, then power consumption and SSO noise are reduced, but switching speed and data transfer efficiency deteriorate
Solution Approach 1:
The patent implements dynamic data bus inversion by comparing the current data word with the previous data word and selectively inverting bits based on the number of transitions. The inversion decision is made dynamically for each data transfer, allowing the system to adapt to actual data patterns rather than using static inversion schemes. This dynamic approach minimizes transitions and reduces power consumption while maintaining high switching speeds.
Solution Approach 2:
The patent changes the inversion parameter adaptively by counting the number of bit transitions between current and previous data words. When the transition count exceeds a threshold, inversion is applied; otherwise, no inversion is performed. This parameter-based adaptive inversion optimizes the balance between power consumption and switching speed by adjusting the inversion behavior based on actual data characteristics.
2Object-affected harmful factors
If data bus inversion is applied to reduce SSO noise, then noise levels decrease, but system complexity increases due to additional control logic
Solution Approach 1:
The patent segments the inversion control logic into distinct functional blocks: a transition counter that compares current and previous data words, a threshold comparator that decides whether inversion is needed, and an inverter that applies the inversion when required. This segmentation of control logic reduces overall system complexity by organizing the inversion management into modular, manageable components with clear interfaces.
Solution Approach 2:
The system performs self-service inversion control by automatically comparing data words and determining when inversion is necessary without external intervention. The transition counter and comparator autonomously monitor data patterns and trigger inversion only when beneficial, eliminating the need for complex external control mechanisms while effectively reducing SSO noise.
3Loss of energy
If adaptive inversion with multiple options is implemented, then power consumption and noise are minimized, but data transfer overhead increases due to additional inversion indication bits
Solution Approach 1:
The patent applies partial inversion by selectively inverting only the necessary bits based on transition counting, rather than inverting entire data words unconditionally. This partial action approach minimizes the number of inverted bits to the exact extent needed to reduce transitions, thereby reducing power consumption without requiring excessive overhead bits for inversion indication.
Data Source
AI summary
An apparatus includes an inversion circuit configured to invert a data word, a first partial-inversion circuit configured to invert a first portion of the data word, a second partial-inversion circuit configured to invert a second portion of the data word, and an output selection circuit configured to compare: the data word, an output of the inversion circuit, an output of the first partial-inversion circuit, and an output of the second partial-inversion circuit with a prior data word, and to select an output according to respective numbers of changed bits from the prior data word.


