Adaptive Write Voltage Control for NAND Flash Over-Programming

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory devices face issues with over-programming due to varying memory cell characteristics over time, leading to defective elements, as the initial write voltage and step-up width are fixed and cannot adapt to changes in cell characteristics.

Innovation Solution

A semiconductor memory device with a control circuit that adjusts the initial write voltage and step-up width based on deterioration information, detected by counting the pulse number of an advance-write voltage, to prevent over-programming and maintain optimal write performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the initial value and step-up width of write voltage are fixed after diesort test, then the write operation can be simplified and device complexity is reduced, but over-program occurs when memory cell characteristics vary due to increased rewrite operations

Engineering Contradiction:
Improvewrite voltage controlVSAvoidwrite operation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent makes the write voltage parameters dynamic by introducing a rewrite counter that tracks the number of rewrite operations. Based on the counter value, the control circuit dynamically adjusts the initial value and step-up width of the write voltage, transitioning from fixed parameters to adaptive parameters that respond to memory cell deterioration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where the rewrite counter monitors the number of rewrite operations and feeds this information back to the control circuit. The control circuit then adjusts the write voltage parameters accordingly, creating a closed-loop system that adapts to memory cell state changes.

Inventive Principle:
Principle #23Feedback

2Productivity

If the number of rewrite operations increases, then memory capacity utilization is improved, but memory cell characteristics vary causing over-program and write defects

Engineering Contradiction:
Improvememory capacity utilizationVSAvoidwrite operation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the write voltage parameters (initial value and step-up width) based on the number of rewrite operations. When the rewrite counter exceeds a threshold, the control circuit modifies these parameters to compensate for memory cell deterioration, thereby maintaining write operation precision despite increased productivity demands.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If fixed write voltage parameters are used, then ease of operation is improved, but defective elements increase due to over-programming in deteriorated memory cells

Engineering Contradiction:
Improvewrite operation controlVSAvoidmemory cell write quality
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent enables the memory device to self-adjust write voltage parameters based on its own operational history. The rewrite counter and control circuit work together to automatically detect memory cell deterioration and compensate by adjusting parameters, making the system self-correcting without external intervention.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7652928B2Semiconductor memory device and control method of the same
Publication Date: 2010.01.26 KIOXIA CORP
  • US7652928B2 patent drawing
  • US7652928B2 patent drawing
  • US7652928B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.