Counter-Transitioning Waveforms for Flash Memory Programming

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Solution Overview

Problem

The programming process in non-volatile semiconductor memory devices, such as NAND flash memory, is hindered by capacitive coupling between neighboring word lines, which causes ripple voltage and delays the verification process, leading to longer programming times.

Innovation Solution

Applying counter-transitioning voltage waveforms to neighboring word lines to counteract capacitive coupling, allowing for simultaneous programming and verification without delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If voltage waveforms are applied to neighboring word lines during programming, then programming operation can be performed, but capacitive coupling causes ripple voltage that delays verification process

Engineering Contradiction:
Improveprogramming speedVSAvoidverification delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary anti-action by transitioning neighboring word lines to a second voltage level before the selected word line voltage transitions, thereby preemptively counteracting the capacitive coupling effect that would otherwise cause ripple voltage and verification delay. This anticipatory action prevents the harmful effect rather than correcting it after occurrence.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent implements preliminary action by preparing the neighboring word lines in advance - transitioning them to the second voltage level before the programming operation on the selected word line begins. This ensures that when the selected word line transitions occur, the capacitive coupling has minimal impact because the neighboring lines are already in their final state.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If verification is performed after programming pulses, then programming accuracy can be ensured, but programming time increases due to sequential operation

Engineering Contradiction:
Improveprogramming verification accuracyVSAvoidprogramming speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent merges the programming and verification operations by allowing them to occur simultaneously. The verification voltage is applied to the bit line during the programming pulse transitions, and the sense amplifier detects the storage element state in real-time. This combines two previously sequential operations into a concurrent process, improving productivity without sacrificing verification accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that verification is continuously performed during the programming process rather than being interrupted. The sense amplifier continuously monitors the storage element state while programming pulses are being applied, eliminating idle time between programming and verification operations.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces capacitive coupling, enabling faster programming and verification, thus enhancing the overall programming speed and efficiency of non-volatile storage elements.

Implementation Method 1

voltage waveforms which are applied to neighboring word lines can be capacitively coupled to the selected word line on which programming occurs

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS7492633B2System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines
Publication Date: 2009.02.17 SANDISK TECHNOLOGIES LLC
  • US7492633B2 patent drawing
  • US7492633B2 patent drawing
  • US7492633B2 patent drawing

AI summary

Non-volatile storage elements are programmed using counter-transitioning waveform portions on neighboring word lines which reduce capacitive coupling to a selected word line. In one approach, the waveform portions extend between pass or isolation voltages of a boosting mode, which are applied during a programming pulse on the selected word line, and read voltages, which are applied when verify pulses are applied to the selected word line to verify whether the storage elements have been programmed to a desired programming state. The waveform portions reduce the net voltage change which is coupled to the selected word line. The selected word line can reach a reduced, steady state level sooner so that the verify pulses can be applied sooner, thus reducing the overall programming time. In another aspect, a pass voltage transitions directly to a read voltage on an unselected word line, thereby reducing programming time.