SONOS Memory Programming via Simultaneous Column Biasing
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Solution Overview
Problem
The existing programming methods for SONOS memory cells are time-consuming and prone to reading errors due to large threshold voltage distributions.
Innovation Solution
Simultaneous programming of memory cells in a selected column by applying multiple biases to word lines and injecting charges through Single Side Bias (SSB) convergence or Double Side Bias (DSB) injection to narrow threshold voltage distributions and reduce programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed one by one using conventional methods, then each memory cell can be individually programmed, but the programming time is very long
Solution Approach 1:
The patent merges multiple individual programming operations into a single simultaneous programming operation by applying a common programming voltage to multiple word lines. This allows memory cells in the same column to be programmed at the same time, significantly reducing total programming time while maintaining reliability through the use of bit line specific voltages to distinguish between different programming targets.
Solution Approach 2:
The patent segments the programming operation into two independent dimensions: word line selection (for parallelism) and bit line selection (for specificity). By separating these functions, the system can apply programming voltage to multiple word lines simultaneously while still targeting specific memory cells through bit line voltage control, resolving the contradiction between speed and accuracy.
2Productivity
If conventional programming methods are used, then programming can be performed, but the threshold voltage distribution is large causing reading errors
Solution Approach 1:
The patent changes the voltage parameters applied during programming by introducing bit line specific voltages in addition to the common word line programming voltage. This parameter modification allows precise control over which memory cells are programmed and to what threshold voltage state, narrowing the threshold voltage distribution and reducing reading errors while maintaining high programming speed.
3Loss of time
If multiple biases are applied to word lines for simultaneous programming, then programming time is reduced, but the device complexity increases
Solution Approach 1:
The patent makes the bit lines serve multiple functions: they act as programming targets during programming operations and as data output lines during read operations. This multi-functionality reduces the need for separate dedicated lines for different operations, minimizing the increase in device complexity while enabling simultaneous programming through bit line specific voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces programming time and narrows the distributions of threshold voltages at various data states, making the memory cells more efficient and reliable.
Implementation Method 1
hole is injected into the memory cells in the selected column through single side bias (SSB) convergence
Implementation Method 2
electron is injected into the memory cells in the memory cells array through double side bias (DSB) electron injection
Implementation Method 3
electron is injected into the memory cells in the memory cells array through Fowler-Nordheim electron tunnelling
Implementation Method 4
hole is injected into the memory cells in the memory cells array through DSB hole injection
Implementation Method 5
hole is injected into the memory cells in the memory cells array through band-to-band tunnelling hot hole injection
Data Source
AI summary
An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.