Memory Array Misalignment Detection and Timing Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D memory devices, misalignments between memory holes and isolation areas can lead to varying resistances in word lines and select gate lines, affecting read and programming performance due to periodic changes in resistance, which reduces the overall read/verify speed and memory device performance.
Innovation Solution
The method involves detecting memory hole/isolation area misalignment and adjusting read/verify operation timing parameters to optimize performance, using techniques such as electrical detection during wafer sort tests and adjusting word line settling time based on detected misalignment patterns to ensure accurate sensing and minimize program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If misalignment between memory holes and isolation areas occurs, then manufacturing variations are introduced, but resistance varies periodically affecting read and programming performance
Solution Approach 1:
The patent applies parameter changes by adjusting timing parameters (read/verify timing, word line settling time) to compensate for resistance variations caused by misalignment. Instead of attempting to eliminate the misalignment itself, the invention changes the operational timing parameters to adapt to the actual resistance conditions in different sub-blocks and blocks, thereby maintaining reliable read and programming performance despite manufacturing variations.
2Productivity
If uniform timing parameters are used for all blocks, then device complexity is reduced, but read and verify speed is reduced due to periodic resistance changes
Solution Approach 1:
The patent applies segmentation by dividing the memory device into different regions (sub-blocks and blocks) with different timing parameters. Instead of using a single uniform timing parameter for the entire device, the invention segments the timing configuration to match the periodic resistance variations across different physical locations, allowing each segment to operate at optimal speed for its specific resistance characteristics.
Solution Approach 2:
The patent applies local quality by assigning different timing parameters to different local regions (sub-blocks and blocks) based on their specific resistance characteristics. Each local region receives customized timing parameters optimized for its particular resistance conditions, rather than applying a one-size-fits-all timing configuration, thereby maximizing overall read and verify speed.
3Measurement precision
If extensive testing is performed on all blocks to determine optimal timing, then measurement precision is improved, but loss of time increases due to testing duration
Solution Approach 1:
The patent applies preliminary action by performing comprehensive timing characterization and testing during the wafer sort test phase, which occurs before the memory devices are packaged and shipped. By completing the time-consuming measurement and optimization process in advance during manufacturing, the invention ensures that when the devices reach the customer, the optimal timing parameters are already configured, eliminating the need for extensive testing at the customer site and reducing overall time loss.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.