NOR Flash Memory Programming via Selective Data Scanning
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Solution Overview
Problem
NOR flash memory devices face high power consumption and limited programming capacity due to the need for high voltage and high program current, restricting the number of memory cells that can be programmed simultaneously, which increases programming time.
Innovation Solution
A method involving a data scanning unit that selectively scans input data bits, combining them into groups to generate combinational information and addresses, allowing only data bits to be programmed from '1' to '0', thereby reducing unnecessary programming operations and optimizing programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to the drain of memory cells for programming, then programming capability is achieved, but power consumption increases and program current exceeds predetermined levels
Solution Approach 1:
The patent segments the 16-bit data into multiple groups (e.g., 4 groups of 4 bits each) and programs them in parallel simultaneously. This segmentation allows the programming operation to be distributed across multiple charge pump circuits, reducing the burden on individual circuits and lowering overall power consumption while maintaining programming capability.
Solution Approach 2:
The patent combines multiple charge pump circuits to operate in parallel, each handling a portion of the data bits. By merging the capabilities of multiple charge pumps working simultaneously, the system achieves the required programming capability while distributing the power consumption across multiple units, preventing any single circuit from exceeding current limits.
2Use of energy by moving object
If the number of memory cells programmed simultaneously is limited due to charge pump capacity, then power consumption is controlled, but programming time increases
Solution Approach 1:
The patent divides the programming task into multiple segments that can be executed in parallel. By segmenting the data and using multiple charge pump circuits to program different segments simultaneously, the total programming time is reduced compared to sequential programming, while each individual charge pump still operates within its power consumption limits.
Solution Approach 2:
The patent transitions from sequential programming (one-dimensional time progression) to parallel programming by adding the dimension of multiple simultaneous charge pump operations. This allows multiple programming operations to occur at the same time, significantly reducing total programming time while maintaining controlled power consumption through the distributed architecture.
3Ease of operation
If all memory cells are programmed regardless of data value, then programming operation is simplified, but unnecessary programming operations increase average programming time
Solution Approach 1:
The patent extracts and identifies only the data bits that actually require programming (those that need to change from '1' to '0') and applies programming operations only to these specific bits. By taking out the unnecessary programming operations for bits that already have the correct value, the system reduces average programming time while maintaining operational simplicity through automated detection.
Solution Approach 2:
The patent applies partial programming action by selectively programming only the necessary portion of data bits rather than all bits. This partial action approach reduces the total programming time by avoiding excessive programming operations on bits that don't need changing, while still ensuring all necessary bits are programmed correctly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes data scanning and programming time by selectively identifying and addressing only the data bits that need to be changed, reducing the average programming time and enhancing the efficiency of NOR flash memory operations.
Implementation Method 1
In programming data into a NOR flash memory, a program command is first applied to the memory device, followed by program addresses and data. The program addresses and data are temporarily stored in the memory device, as well as a memory cell assigned to the program address. A program voltage corresponding to the program data is applied to the bitline, and then an actual programming operation is carried out.
Implementation Method 2
A NOR flash memory has a memory cell array in which more two cell transistors are connected to in parallel to a bitline. Data is stored by means of channel hot electron effects and erased means of the Fowler-Nordheim (F-N) tunneling effect.
Data Source
AI summary
A nonvolatile memory device is programmed by selectively scanning input data bits to detect data bits to be programmed, and programming the detected data bits. The detected data bits may be programmed in predetermined units. The input data bits may be selectively scanned by combining input data bits in groups, thereby generating combinational information, and generating address information in response to the combinational information.