Word Line Block Select Circuit with Dummy Repair Logic
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Solution Overview
Problem
Conventional semiconductor memory devices face significant delays and processing margins in tRCD measurements due to variable time delays, leading to inefficiencies and tRCD loss when deciding whether to activate redundancy or normal word lines.
Innovation Solution
A word line block select circuit with a dummy repair logic unit that generates a first control signal, mirroring the delay path of the repair address decision unit, allowing direct compensation for time delays without additional margins, thereby stabilizing operations and reducing time losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay chain with additional delay paths and metal options is used to compensate for time delay in the repair address decision unit, then the circuit can handle variable delays, but the processing margin increases by several nanoseconds causing tRCD deterioration
Solution Approach 1:
The patent creates a dummy repair logic unit that is an exact copy of the repair address decision unit, including identical delay paths. This dummy unit generates a control signal that mirrors the timing characteristics of the actual repair decision, allowing the normal word line activation to be properly synchronized without adding excessive delay margins.
Solution Approach 2:
The dummy repair logic unit performs preliminary timing synchronization by generating the control signal in advance with the correct delay characteristics. This allows the normal word line decoder to be activated at the appropriate time without waiting for the actual repair decision, thus reducing tRCD while maintaining stable operation.
2Reliability
If a processing margin of several nanoseconds is taken to ensure stable operation, then reliable word line selection is achieved, but time loss increases and tRCD performance deteriorates
Solution Approach 1:
By copying the exact delay path structure from the repair address decision unit to the dummy repair logic unit, the patent eliminates the need for additional processing margins. The control signal generated by the dummy unit inherently accounts for all timing variations, allowing tight timing without sacrificing reliability.
3Reliability
If metal option correction is performed to fix simultaneous activation of redundancy and normal word lines, then circuit stability is improved, but additional time loss occurs
Solution Approach 1:
The dummy repair logic unit performs preliminary timing synchronization to prevent the simultaneous activation problem before it occurs. By generating the control signal with precise timing based on the copied delay path, the patent eliminates the need for post-correction metal option adjustments, thus avoiding additional time loss.
Data Source
AI summary
A word line block select circuit includes a dummy repair logic unit including a dummy logic circuit to output a first control signal and having a delay path for a repair address decision, and a word line activation unit for activating a word line in response to the first control signal and an active command signal.