NAND Flash Memory Controller Shift Read Error Diagnosis

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Solution Overview

Problem

NAND-type flash memory systems face issues with data retention deterioration, program disturb, and read disturb, leading to unnecessary refresh operations and capacity reduction, as conventional techniques often invalidate memory areas without distinguishing the cause of errors.

Innovation Solution

A memory system with a memory controller that includes a shift read controller, threshold voltage distribution acquisition module, comparison module, and error factor determination module to differentiate between error causes, thereby inhibiting unnecessary data moves and refreshing only when necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional refresh operation is performed to correct read errors, then data reliability is improved, but memory cell deterioration accelerates and useful capacity decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoidmemory life
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent changes the parameter of read voltage by performing multiple reads with different read voltages (first read voltage and second read voltage different from each other). This allows differentiation between errors caused by program disturb (corrected by voltage change) and other errors (not corrected), enabling selective refresh operations that avoid unnecessary writes and extend memory life while maintaining data reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system uses the memory cells themselves to indicate their error status through threshold voltage characteristics. By reading at different voltages and observing whether errors are corrected, the memory system self-identifies which cells need refresh without external intervention, allowing precise control of refresh operations to minimize wear

Inventive Principle:
Principle #25Self-service

2Reliability

If conventional refresh operation is performed to correct read errors, then data reliability is improved, but device complexity increases due to unnecessary data moves

Engineering Contradiction:
Improvedata reliabilityVSAvoidrefresh operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a parameter change approach by performing reads at different voltages to classify errors. This simple voltage variation method provides rich diagnostic information about error causes without requiring complex analysis circuits or additional hardware, maintaining low device complexity while improving reliability through intelligent refresh selection

Inventive Principle:
Principle #35Parameter changes

3Reliability

If memory area is invalidated after refresh to prevent errors, then data reliability is improved, but useful capacity decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoiduseful capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by treating different memory areas differently based on their error characteristics. Instead of invalidating entire memory areas, it identifies specific cells with program disturb errors through voltage-dependent read behavior and performs refresh only on those local regions. This preserves useful capacity by keeping error-free areas active while maintaining reliability through targeted correction

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9189313B2Memory system having NAND-type flash memory and memory controller with shift read controller and threshold voltage comparison module
Publication Date: 2015.11.17 KIOXIA CORP
  • US9189313B2 patent drawing
  • US9189313B2 patent drawing
  • US9189313B2 patent drawing

AI summary

According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.