Sense Amplifier Node TDC for NAND Flash Read Speed
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Solution Overview
Problem
Current NAND flash memory devices face challenges in enhancing read operation speed and preventing erroneous data determination during digitizing, primarily due to limitations in amplifying voltage differences and controlling latch circuits.
Innovation Solution
The semiconductor memory device incorporates a sense amplifier with a node TDC for amplifying voltage differences between the node SEN and threshold voltages, allowing for digitizing without controlling latch circuits, thereby reducing operation time and preventing erroneous determinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sense amplifier circuits are used for digitizing, then the device area increases due to additional latch circuits, but the read operation speed is improved
Solution Approach 1:
The patent extracts the digitizing function from the conventional sense amplifier circuit by introducing a separate first circuit (comprising first, second, and third transistors) that performs voltage difference amplification. This separation allows the main sense amplifier to focus on sensing while the extracted digitizing circuit handles conversion, improving speed without requiring additional latch circuits in the original sense amplifier structure.
Solution Approach 2:
The first circuit serves multiple functions: it amplifies voltage differences between the SEN node and threshold voltages, performs digitizing conversion, and outputs results to the bit line. This multi-functional design eliminates the need for separate latch circuits, reducing device area while maintaining high read operation speed.
2Measurement precision
If voltage difference amplification is enhanced for accurate digitizing, then measurement precision improves, but the device complexity increases
Solution Approach 1:
The patent applies local quality by creating a dedicated first circuit with specific transistor configurations (first transistor with gate coupled to SEN node, second transistor coupling intermediate and output nodes, third transistor with gate coupled to output node) that locally performs high-precision voltage difference amplification. This localized precision circuitry avoids the need for complex global circuit redesign, maintaining overall simplicity while achieving high measurement precision.
Solution Approach 2:
The circuit achieves enhanced voltage difference amplification by changing the operational parameters of the transistor network, specifically utilizing the gate-coupled configurations to create amplification stages that boost voltage differences between the SEN node and threshold voltages, thereby improving digitizing accuracy without increasing structural complexity.
3Reliability
If latch circuits are controlled for digitizing, then data determination accuracy improves, but the operation time increases
Solution Approach 1:
The first circuit performs preliminary voltage difference amplification and digitizing conversion before the main sense amplifier completes its sensing operation. By preparing the digitized signal in advance through the first, second, and third transistor stages, the circuit enables faster data determination without requiring subsequent latch circuit control, thereby reducing operation time while maintaining accuracy.
Solution Approach 2:
The second transistor acts as an intermediary element that couples the intermediate node and output node, facilitating smooth signal transfer and amplification. This intermediary structure enables accurate voltage difference conversion without the need for complex latch circuit control mechanisms, reducing operation time while preserving data determination accuracy.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.