Semiconductor Memory Device Erase Voltage Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently executing erase operations, particularly in maintaining voltage differences across various wiring and transistors to ensure high-speed erase operations without causing threshold voltage variations in select transistors.
Innovation Solution
The semiconductor memory device incorporates a control circuit that maintains specific voltage differences between various wirings and transistors during an erase operation. This includes controlling the voltage of the first wiring to be larger than the third wiring, and the voltage of the third wiring to be larger than the fourth wiring, while ensuring the voltage differences between the first and third, and third and fourth wirings remain constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage differences are increased to accelerate erase operation, then erase speed is improved, but threshold voltage variations in select transistors increase causing malfunctions
Solution Approach 1:
The patent applies different voltage levels to different transistors in the memory string. Specifically, the first select transistor receives a first voltage level, the second select transistor receives a second voltage level, and the memory transistor receives a third voltage level. This local differentiation allows the erase operation to proceed at high speed while preventing excessive voltage stress on any single transistor, thereby maintaining threshold voltage stability.
Solution Approach 2:
The patent dynamically adjusts voltage parameters during the erase operation. By controlling the voltage levels applied to different transistors (first voltage level for first select transistor, second voltage level for second select transistor, third voltage level for memory transistor), the system optimizes the erase speed while preventing threshold voltage variations that would cause malfunctions.
2Adaptability or versatility
If multiple transistors are connected in series to enable selective access, then memory functionality is improved, but voltage control complexity increases
Solution Approach 1:
The patent segments the memory string into distinct functional units with dedicated control: first select transistor for data input control, second select transistor for readout control, and memory transistor for data storage. Each segment is controlled by a dedicated wiring (first wiring, second wiring, third wiring respectively), allowing independent voltage control and simplifying the overall control logic despite the series connection.
Solution Approach 2:
The patent employs a control circuit that can generate multiple voltage levels using the same basic circuitry. The control circuit applies different voltage levels to different transistors based on the operation mode (erase, read, write), making the voltage control system versatile and adaptable to various operations without requiring separate control circuits for each transistor.
Data Source
AI summary
A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.