Semiconductor Memory Leak Current Detection and Block Isolation
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Solution Overview
Problem
Miniaturization of memory cells in semiconductor memory devices leads to short-circuit faults between wiring lines or between a wiring line and the semiconductor substrate, which are difficult to detect in pre-shipment tests and can deteriorate into faults during user usage.
Innovation Solution
A semiconductor memory device with a leak current detecting circuit that registers memory blocks with excessive leak current as access-prohibited regions, based on the number of access operations or error bit counts, to prevent data destruction and ensure operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase storage density, then storage capacity is improved, but short-circuit faults between wiring lines or between wiring line and substrate increase
Solution Approach 1:
The patent performs preliminary detection of leak current during the access operation phase, before the short-circuit fault can cause data destruction. By detecting the leak current at this early stage and executing faulty memory block processing to isolate the defective block, the system prevents the fault from escalating and ensures continuous reliable operation.
2Manufacturing precision
If pre-shipment test is performed to detect short-circuit faults, then manufacturing quality is improved, but defects that manifest during user usage remain undetected
Solution Approach 1:
The patent extends the detection process from the manufacturing phase into the operational phase by continuously monitoring leak current during access operations. This continuous monitoring ensures that defects which may not manifest during pre-shipment testing but develop during normal usage are detected and addressed promptly, maintaining high reliability throughout the product lifecycle.
3Reliability
If leak current detection is performed during access operation, then post-shipment defects are detected, but device complexity increases
Solution Approach 1:
The patent makes the existing control circuit perform multiple functions: it not only controls normal memory access operations but also simultaneously detects leak current and identifies faulty memory blocks. By having the control circuit serve both operational and detection purposes, the patent avoids adding separate dedicated detection hardware, thereby limiting the increase in device complexity while achieving reliable post-shipment defect detection.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including a memory block, the memory block including a memory cell, the memory cell including a semiconductor layer, a conductive layer, and a charge accumulation layer, the charge accumulation layer being disposed between the semiconductor layer and the conductive layer; and a control circuit that executes an access operation on the memory cell, the control circuit, triggered by the access operation, detecting a leak current of the conductive layer, and when the leak current is a certain value or more, executing a faulty memory block processing that registers as an access-prohibited region the memory block including the conductive layer.