Memory Device Ramp Voltage Biasing for Multi-Level Cell Reading
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Solution Overview
Problem
Existing memory devices face challenges in accurately reading multi-level memory cells due to the complexity and slowness of ramp generators, leading to increased reading time and area waste in semiconductor chips.
Innovation Solution
An open-loop design is implemented using a biasing current with a constant slope to generate a monotone time-patterned biasing voltage, reducing chip area waste and increasing reading speed by applying a predetermined biasing current to both selected and reference memory cells, with optional equalization of resistance and capacitance to minimize voltage mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a closed-loop ramp generator with feedback regulation is used to generate biasing voltage, then the accuracy and repeatability of the biasing voltage is improved, but the device complexity and chip area increase
Solution Approach 1:
The patent extracts the feedback regulation mechanism from the ramp generator, eliminating the complex closed-loop control circuitry while maintaining voltage accuracy through an open-loop current source design that inherently provides stable biasing voltage
Solution Approach 2:
The current source circuit performs multiple functions: it generates the ramp voltage, provides feedback regulation, and biases both memory and reference cells simultaneously, replacing what would traditionally require separate dedicated circuits
2Measurement precision
If a closed-loop ramp generator with feedback regulation is used to generate biasing voltage, then the accuracy of the biasing voltage is improved, but the reading time increases
Solution Approach 1:
The current source is pre-configured with predetermined current values that correspond to different logical states, allowing the ramp voltage to immediately begin its linear increase without requiring real-time feedback adjustment during the reading operation
Solution Approach 2:
The patent implements dynamic current switching that allows the biasing current to change slope at predetermined points during the ramp cycle, enabling the system to adapt to different reading requirements while maintaining overall speed
3Speed
If a high slope of biasing voltage is used to reduce reading time, then the reading speed is improved, but the accuracy of the biasing voltage pattern decreases
Solution Approach 1:
The patent changes the current slope parameter at predetermined points during the ramp cycle, allowing the system to use higher slopes for faster reading while maintaining accuracy through pre-calibrated current transitions that occur at specific voltage thresholds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a simpler, faster memory device with reduced reading time and improved performance by allowing a high slope of the biasing voltage, enhancing the accuracy and speed of data retrieval in multi-level memory devices.
Implementation Method 1
The memory device further includes means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell
Implementation Method 2
each memory cell has a threshold voltage that can be programmed to different levels representing corresponding logical values
Data Source
AI summary
A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.