Nonvolatile Memory Page Buffer Simultaneous Latch Setting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile semiconductor memory devices face inefficiencies in program verification operations, leading to increased cycle counts and power consumption due to the sequential setting of data latches in page buffers.
Innovation Solution
The implementation of a nonvolatile memory device with a page buffer unit that allows simultaneous setting of data latches in multiple page buffers using a set pulse, reducing the number of operating cycles and power consumption during program verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data latches in page buffers are set sequentially during program verification, then the operation is simple to control, but the number of operating cycles increases and power consumption increases
Solution Approach 1:
The patent merges the control of multiple page buffers by applying a single set pulse signal simultaneously to multiple page buffers. This allows data latches in different page buffers to be set at the same time during program verification, reducing the total number of operating cycles while maintaining controllable operation through unified signal management
2Use of energy by stationary object
If data latches in page buffers are set sequentially, then the control logic is simple, but power consumption increases due to increased cycle counts
Solution Approach 1:
The patent employs periodic pulsed action by using a set pulse signal that is applied simultaneously to multiple page buffers. This pulsed simultaneous setting reduces the total time required for program verification compared to sequential setting, thereby reducing power consumption since power is consumed only during the active pulse periods rather than continuously across multiple sequential cycles
3Productivity
If sequential setting of data latches is used, then device operation is straightforward, but the number of operating cycles increases
Solution Approach 1:
The patent combines the data latch setting operation across multiple page buffers by applying a unified set pulse signal simultaneously to all relevant page buffers. This merging of operations reduces the total number of operating cycles required for program verification, thereby improving program operation efficiency without requiring complex individual control for each page buffer
Data Source
AI summary
A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.