One-Time Programmable Latch Circuit Area Reduction
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Solution Overview
Problem
Conventional programmable latch circuits require large nonvolatile devices and occupy significant area due to the need for two OTP devices for redundancy, making them inefficient in terms of size and programming current requirements.
Innovation Solution
A programmable latch circuit design that utilizes a single one-time programmable (OTP) device with a current source providing a reference current, allowing data to be stored and loaded into a latch circuit, and includes redundancy with an additional OTP device for fault tolerance, using gate oxide anti-fuse devices and insulated gate field effect transistors to manage current and voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programmable latch circuits use two OTP devices for redundancy, then fault tolerance is improved, but circuit area and programming current requirements worsen
Solution Approach 1:
The patent combines the functions of two separate OTP devices into a single OTP device by implementing redundancy at the circuit level rather than the device level. The single OTP device is paired with specially designed latch circuitry that provides fault tolerance through internal redundancy mechanisms, thereby reducing the total device count and circuit area while maintaining reliability.
Solution Approach 2:
The latch circuit is designed to serve multiple functions: it provides data storage, fault tolerance, and programming capabilities using a single OTP device. The circuit architecture enables the same hardware to achieve both redundancy and compactness by integrating error correction and fault tolerance features directly into the latch operation rather than requiring separate dedicated devices.
2Reliability
If conventional programmable latch circuits use two OTP devices, then redundancy is improved, but programming current requirements worsen
Solution Approach 1:
The patent merges the programming functions for two redundant devices into a single programming operation for one OTP device. The circuit architecture allows the same programming current to be utilized more efficiently by the single device while the latch circuitry provides the redundancy, thereby reducing total programming current requirements.
Solution Approach 2:
Instead of programming two physical OTP devices, the patent creates a logical copy or representation of redundancy through the latch circuit design. The single OTP device's state is replicated or protected through circuit-level mechanisms that simulate the effect of having two devices without requiring the actual hardware duplication and associated programming current.
3Area of stationary object
If a single OTP device is used, then circuit area is reduced, but fault tolerance worsens
Solution Approach 1:
The patent implements nested redundancy where fault tolerance mechanisms are embedded within the latch circuit architecture itself rather than requiring external or separate redundancy devices. The latch circuit contains internal redundancy structures that protect the single OTP device's data, creating a nested hierarchy of protection that maintains reliability while minimizing area.
Solution Approach 2:
The latch circuit acts as an intermediary between the single OTP device and the external environment, providing fault tolerance through its internal design. The latch circuitry mediates the storage and retrieval operations, incorporating error detection and correction mechanisms that protect against faults without requiring additional OTP devices, thus maintaining reliability while using minimal area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design results in a compact circuit size with reduced area requirements and improved redundancy, enabling efficient data storage and retrieval while maintaining data integrity even after power removal.
Implementation Method 1
A programmable latch circuit design that utilizes a single one-time programmable (OTP) device with a current source providing a reference current, allowing data to be stored and loaded into a latch circuit, and includes redundancy with an additional OTP device for fault tolerance, using gate oxide anti-fuse devices and insulated gate field effect transistors to manage current and voltage effectively.
Data Source
AI summary
A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.