Parallel Input Circuit Training in Semiconductor Memory Devices
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in data transfer rates due to serial execution of training methods with memory core operations, leading to increased operation times and reduced performance.
Innovation Solution
Incorporating a training circuit that executes input circuit training in parallel with memory core operations, such as read, write, and erase operations, allowing for concurrent adjustment of skew, reference voltage, and impedance settings, and enabling the training to start during busy states indicated by the ready/busy signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If training is executed serially with memory core operations, then training can be completed thoroughly, but overall operation time increases and productivity decreases
Solution Approach 1:
The training circuit performs input circuit training in advance or concurrently with memory core operations by utilizing the ready/busy signal timing. Training is executed during periods when the memory core is naturally busy with read/write/erase operations, thereby preparing the input circuit before actual data transfer without delaying overall operation completion.
Solution Approach 2:
The training circuit operates continuously in parallel with memory core operations by monitoring the ready/busy signal. When the memory core is busy (ready/busy signal indicates busy state), training proceeds concurrently; when the memory core is idle, training completes or waits seamlessly, ensuring continuous useful action without interruption to overall system productivity.
2Productivity
If training is executed in parallel with memory core operations, then productivity improves, but timing coordination complexity increases
Solution Approach 1:
The training circuit uses the ready/busy signal as feedback to automatically coordinate its operation with the memory core. The ready/busy signal provides real-time information about the memory core's state, enabling the training circuit to start, pause, or complete training at appropriate moments without complex external timing control logic.
Solution Approach 2:
The training circuit autonomously manages its own execution timing by internally monitoring the ready/busy signal and self-regulating its operation accordingly. This self-service mechanism eliminates the need for external controllers to manage timing coordination, reducing overall system complexity while maintaining parallel operation capability.
3Loss of time
If training starts during busy states, then time overlap is minimized, but training may be interrupted or delayed
Solution Approach 1:
The training circuit dynamically adjusts its operation based on the memory core's real-time state indicated by the ready/busy signal. Training can start during busy states when time overlap is acceptable, and the circuit is designed to handle potential interruptions or delays by resuming or completing training when conditions permit, ensuring both time efficiency and execution reliability.
Solution Approach 2:
The training circuit incorporates timing margins and flexible scheduling to cushion against potential interruptions when starting training during busy states. By designing the training sequence with built-in time buffers and the ability to adapt to delays, the system ensures reliable training execution even when starting during periods of memory core activity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.